Denso Corporation

Nippondenso Co., Ltd.

Sumco Corporation

Denso Corpora Tion

Sumitomo Mitsubishi Silicon Corporation

Hitoshi Yamaguchi

Jun Sakakibara

Shoichi Yamauchi

Yoshiyuki Hattori

Tsuyoshi Yamamoto

Yasushi Urakami

Toshiyuki Morishita

Takumi Shibata

Tetsuo Fujii

Toshio Sakakibara

Masakiyo Sumitomo

Tomoatsu Makino

Naohiro Suzuki

Nozomu Akagi

Tomonori Yamaoka

Syouji Nogami

Nobuhiro Tsuji

Shoji Mizuno

Takeshi Miyajima

Hiroaki Himi

Makoto Kuwahara

Mikimasa Suzuki

Seiji Fujino

Kyoko Okada

Yuma Kagata

Yoshitaka Noda

Rie Taguchi

Hirotaka Saikaku

Tadashi Hattori

Takashi Suzuki

Masaru Hori

Toshimasa Yamamoto

Kyoko Nakashima

A plurality of synapse determination circuits are provided on a one-to-one basis for a plurality of gate electrodes of a multi-input gate electrode in a neuron element. With respect to first image regions where '1' is repeatedly inputted in correspondence with group information, the synapse determination circuits corresponding to the first image regions are excitatory synapses. With respect to second image regions where '0' is repeatedly inputted in correspondence with the group information, the synapse determination circuits corresponding to the second image regions are inhibitory synapses.

Group information storing and recognizing apparatus

A semiconductor photocatalyst includes first and second layers made of first and second materials, respectively. Band gaps of the first and second materials are equal to or smaller than 1.5 eV and 2.5 eV, respectively. A lower electric potential of a conduction band of the second material is disposed on a positive side from the first material. An upper electric potential of a valence band of the second material is disposed on a positive side from the first material and from an oxidation electric potential of water when the first and second layers are bonded to each other in the hetero junction manner. The lower electric potential of the conduction band of the first layer is disposed on a negative side from a reduction electric potential of hydrogen when the first and second layers are bonded to each other in the hetero junction manner.

Semiconductor photocatalyst and artificial photonic synthesis device having the same

A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

Semiconductor device having switching element and free wheel diode and method for controlling the same

A method for manufacturing a semiconductor device includes the steps of: forming a trench in a semiconductor substrate; and forming an epitaxial film on the substrate including a sidewall and a bottom of the trench so that the epitaxial film is filled in the trench. The step of forming the epitaxial film includes a final step before the trench is filled with the epitaxial film. The final step has a forming condition of the epitaxial film in such a manner that the epitaxial film to be formed on the sidewall of the trench has a growth rate at an opening of the trench smaller than a growth rate at a position of the trench, which is deeper than the opening of the trench.

Method for manufacturing semiconductor device

A semiconductor device includes: a substrate; multiple first and second conductive type regions on the substrate for providing a super junction structure; a channel layer on the super junction structure; a first conductive type layer in the channel layer; a contact second conductive type region in the channel layer; a gate electrode on the channel layer via a gate insulation film; a surface electrode on the channel layer; a backside electrode on the substrate opposite to the super junction structure; and an embedded second conductive type region. The embedded second conductive type region is disposed in a corresponding second conductive type region, protrudes into the channel layer, and contacts the contact second conductive type region. The embedded second conductive type region has an impurity concentration higher than the channel layer, and has a maximum impurity concentration at a position in the corresponding second conductive type region.

Semiconductor device and manufacturing method of the same

A semiconductor device includes a substrate, a plurality of first columns having a first conductivity type, a plurality of second columns having a second conductivity type, a first electrode, and a second electrode. The first columns and the second columns are alternately arranged on the substrate to provide a super junction structure. The first electrode is disposed on the super junction structure, forms schottky junctions with the first columns, and forms ohmic junctions with the second columns. The second electrode is disposed on the substrate on an opposite side of the super junction structure. At least a part of the substrate and the super junction structure has lattice defects to provide a lifetime control region at which a lifetime of a minority carrier is controlled to be short.

Semiconductor device including schottky barrier diode and method of manufacturing the same

A semiconductor device includes an insulated gate transistor and a resistor. The insulated gate transistor includes a plurality of first cells for supplying electric current to a load and a second cell for detecting an electric current that flows in the first cells. A gate terminal of the plurality of first cells is coupled with a gate terminal of the second cell and a source terminal of the plurality of first cells is coupled with a source terminal of the second cell on a lower potential side. The resistor has a first terminal coupled with a drain terminal of the second cell and a second terminal coupled with a drain terminal of the first cells on a higher potential side. A gate voltage of the insulated gate transistor is feedback-controlled based on an electric potential of the resistor.

Semiconductor device including a plurality of cells

A semiconductor device having a super junction MOS transistor includes: a semiconductor substrate; a first semiconductor layer on the substrate; a second semiconductor layer on the first semiconductor layer; a channel forming region on a first surface portion of the second semiconductor layer; a source region on a first surface portion of the channel forming region; a source contact region on a second surface portion of the channel forming region; a gate electrode on a third surface portion of the channel forming region; a source electrode on the source region and the source contact region; a drain electrode on a backside of the substrate; and an anode electrode on a second surface portion of the second semiconductor layer. The anode electrode provides a Schottky barrier diode.

Semiconductor device having super junction MOS transistor and method for manufacturing the same

A semiconductor apparatus is disclosed. The semiconductor apparatus includes a semiconductor substrate that has a first surface and a second surface opposite to each other. The semiconductor apparatus further includes multiple double-sided electrode elements each having a pair of electrodes located respectively on the first and second surfaces of the semiconductor substrate. A current flows between the first and second electrode. Each double-sided electrode element has a PN column region located in the semiconductor substrate. The semiconductor apparatus further includes an insulation trench that surrounds each of multiple double-sided electrode elements, and that insulates and separates the multiple double-sided electrode elements from each other.

Semiconductor apparatus including a double-sided electrode element and method for manufacturing the same

A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench, the first and second columns alternately repeated along with a predetermined direction; thinning a second side of the substrate; and increasing an impurity concentration in a thinned second side so that a first conductive type layer is provided. The impurity concentration of the first conductive type layer is higher than the first column. The first column provides a drift layer so that a vertical type first-conductive-type channel transistor is formed.

Method for manufacturing a vertical transistor that includes a super junction structure

A semiconductor device includes: a first semiconductor layer; a PN column layer having first and second column layers; and a second semiconductor layer. Each of the first and second column layers includes first and second columns alternately arranged along with a horizontal direction. The first and second column layers respectively have first and second impurity amount differences defined at a predetermined depth by subtracting an impurity amount in the second column from an impurity amount in the first column. The first impurity amount difference is constant and positive. The second impurity amount difference is constant and negative.

Semiconductor device having super junction

A semiconductor device includes: a first semiconductor layer; a p-n column portion over the first semiconductor layer and including second and third semiconductor layers, which are alternately arranged; and a peripheral portion adjacently to the p-n column portion and including a fourth semiconductor layer. An end second semiconductor layer has an impurity amount equal to or larger than a half of other second semiconductor layers. The third semiconductor layers include a large impurity amount portion adjacent to the end second semiconductor layer. The large impurity amount portion includes at least one third semiconductor layer having an impurity amount larger than an impurity amount of other third semiconductor layers.

Semiconductor device having p-n column portion

A semiconductor device includes: a MOS transistor; a protection diode; and a semiconductor substrate. The MOS transistor and the protection diode are disposed in the semiconductor substrate. The drain of the MOS transistor is connected to the cathode of the protection diode. The source of the MOS transistor is connected to the anode of the protection diode. The MOS transistor has a withstand voltage defined as V. The protection diode has a withstand voltage defined as V, a parasitic resistance defined as R, and a maximum current defined as I. They satisfy a relationship of V&#x3e;V+I&#xd7;R. The maximum current of Iis equal to or larger than 45 Amperes.

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Nisshin, Japan

Hitoshi Yamaguchi