Fujitsu Corporation

Fujitsu Microelectronics Limited

Hitoshi Watanabe

Akio Yamada

Koji Abe

Manabu Ohno

Kiichi Sakamoto

Katsuhiko Kobayashi

Kenichi Kawakami

Satoru Yamazaki

Masahiro Sano

Satoru Sagou

Koichi Itaya

Toshihito Shimizu

Hiroshi Yasuda

Yasushi Takahashi

Yoshihisa Oae

Kenichi Miyazawa

Tomohiko Abe

Junichi Kai

Takamasa Satoh

Soichiro Arai

Ryuji Shimizu

Hideaki Konishi

Kazuyuki Yamamura

Osamu Ōkano

Junko Kumagai

Seiko Oosaki

Yuko Katoh

Naoko Karasawa

Takeshi Doi

Daisuke Tsukuda

An apparatus for supporting verification includes a detecting unit that detects description data of a false path from setting data for a system mode operation of a target circuit to be verified; an analyzing unit that analyzes the description data in the system mode operation and a test mode operation of the target circuit; a diversion determining unit that determines, based on a result of analysis by the analyzing unit, whether the description data is divertible to the test mode operation; and a generating unit that generates setting data for the test mode operation based on a result of determination by the determining unit.

Method and apparatus for supporting verification, and computer product

A frame input unit receives an input of a frame having a placement area for an element to which a predetermined signal is supplied. A netlist input unit receives an input of a netlist concerning the element. A placing unit places the element in the placement area of the frame input by the frame input unit based on the netlist input by the netlist input unit. A detecting unit detects whether there is a vacant position in the placement area in which the element is placed by the placing unit, and a bypass-element placing unit places a bypass element at the vacant position detected by the detecting unit, the bypass element propagating the predetermined signal by bypassing the element located adjacent to the vacant position.

Layout design apparatus, layout design method, and computer product

A verifying method and apparatus verifies operation of a semiconductor circuit device by inputting, to a logical simulator, logical models representing a logic circuit and an analog circuit, adding, to the logical model representing the analog circuit, a function that generates a function value in accordance with the state of connections between terminals of the analog circuit and terminals of the logic circuit, outputting the result of comparing the function value generated by the function and an expected value, and, based on a result of the comparison, determining whether or not there is a connection error between the terminals of the analog circuit and the terminals of the logic circuit.

Semiconductor-circuit-device verifying method and CAD apparatus for implementing the same

A design support apparatus includes a unit that inputs a user net list created by using hard macro cells excluding test circuits, and a unit that arranges hard macro cells using a frame into which hard macro cells, where timing-converged physical information includes test terminals, and test circuits are embedded as arrangement/wiring information. Moreover, includes a unit that arranges and wires the test circuits using the arrangement/wiring information of the test circuit embedded into the frame, a unit that recognizes arrangement/wiring information where the arrangement/wiring information of the test circuits is removed from arrangement/wiring information obtained by wiring, and a unit outputs a net list of a logic structure.

Method and apparatus for supporting designing of LSI, and computer product

A layout designing apparatus includes an input unit that receives an input of a frame having a boundary scan register, a placing unit that places an I/O macro to be connected to a signal terminal for propagating other signal than a test signal in an arbitrary I/O macro placement area of the frame input, a determining unit that determines whether a frame terminal at an arbitrary terminal position in the frame matches with at least one of a test terminal for propagating the test signal in the frame input and a signal terminal to be connected to the I/O macro placed, and a replacing unit that replaces, based on a result of determining by the determining unit, the I/O macro placed with either of a shared I/O macro and a test-only I/O macro.

Method and apparatus for designing layout, and computer product

A test data generating system and method to conduct high-speed operation (actual operation) test of an LSI using a tester. The system converts existing simulation data to high-speed operation verifying test data which is formed to obtain a predetermined output expectation value after a clock signal is stopped for a predetermined period. The test data generating system includes a selecting device to select first output expectation values from simulation data and an inserting device to insert output expectation values, which are identical to a predetermined number of the first expectation values, after the first output expectation values. The system also inserts an input pattern, which is identical to a predetermined number of the input patterns, after the input pattern corresponding to the first output expectation value. A replacing device replaces the predetermined output expectation values of the simulation data with third output expectation values, and a setting device sets the first output expectation values to second output expectation values determined from the simulation data based on the predetermined number or the third output expectation values.

Test data generating system and method to test high-speed actual operation

A test data generating system and method to conduct high-speed operation (actual operation test of an LSI using a tester. The system converts existing simulation data to high-speed operation verifying test data which is formed to obtain a predetermined output expectation value after a clock signal is stopped for a predetermined period. The test data generating system includes a selecting device to select first output expectation values from simulation data and an inserting device to insert output expectation values, which are identical to a predetermined number of the first expectation values, after the first output expectation values. The system also inserts an input pattern, which is identical to a predetermined number of the input patterns, after the input pattern corresponding to the first output expectation value. A replacing device replaces the predetermined output expectation values of the simulation data with third output expectation values, and a setting device sets the first output expectation values to second output expectation values determined from the simulation data based on the predetermined number or the third output expectation values.

A method of detecting deficiency of an aperture used in a charged-particle-beam exposure process employing at least two exposure columns is disclosed, where each of the two exposure columns passes a charged-particle beam through the aperture formed through a mask to shape a cross section of the charged-particle beam before exposing the charged-particle beam onto an object. The method includes the steps of mounting masks having the same aperture to the at least two exposure columns; scanning, in each of the at least two exposure columns, the charged-particle beam over an area containing a mark on a surface substantially at the same height as the object after passing the charged-particle beam through the same aperture; obtaining, in each of the at least two exposure columns, a signal waveform corresponding to the scan by detecting charged particles scattered by the mark; and comparing the signal waveform between the at least two exposure columns.

Charged-particle-beam exposure device and charged-particle-beam exposure method

Charged particle-beam exposure device and charged-particle-beam exposure

By using a blanking aperture array BAA, the density of the bit map data in the portions where adjacent areas are linked is decreased toward the outside. On the lower surface of the holder of the BAA chip, a ball grid array wired to blanking electrodes is formed, to be pressed in contact against pads on a wiring base board. The registered bit map data for an isosceles right triangle are read out from address A=A0+�RA.multidot.i! (A0 and i are integers, � ! is an operator for integerizing), masked, and then shifted by bits to be deformed. From registered bit map data for proximity effect correction, the area which corresponds to the size of the object of correction and the required degree of proximity affect correction is extracted, and logic operation with the bit map data of the object of correction is performed to achieve proximity affect correction. Before figures data are expanded into bit map, a checksum is determined in units of bit map data corresponding to the range of one session of scanning over which continuous exposure is possible. A sine wave voltage is provided to an electrostatic deflector and during a one-shot exposure period, an electron beam is caused to scan for an integer number of times on a block of a mask and the positional misalignment of the electron beam at the lower aperture stop is corrected.

Method of and system for exposing pattern on object by charged particle

Method of detecting a deficiency in a charged-particle-beam exposure mask

Growing community of inventors

Kawasaki, Japan

Hitoshi Watanabe