Hitachi, Ltd.

Hitachi Software Engineering Company, Ltd.

Hitachi Computer Engineering Co., Ltd.

Hitoshi Ueno

Yukari Hatta

Yutaka Uematsu

Satoru Watanabe

Takayuki Ono

Hideki Osaka

Akio Idei

Satoshi Muraoka

Masabumi Shibata

Michinori Naito

Yuichi Fukuda

Takashi Miyagawa

Hiroshi Kakita

Taishi Sumikura

Yuusuke Fukumura

Ken'ichi Soejima

Masaaki Ohya

Narishige Morimoto

Masaki Sato

Takao Satoh

Toshio Hirosawa

Toshiaki Arai

Yoshihiro Kondo

Tomoki Sekiguchi

Kouji Masuda

Toshiyuki Kinoshita

Sachie Tajima

Kazunori Nakajima

Jun'ichi Kurihara

Masahiro Kitano

Ikuo Kimura

Akira Ando

Masahiko Ishimaru

Masaichiro Yoshioka

Yoshikazu Ichikawa

Tetsuji Ogawa

Satoshi Oguni

Yusuke Fukumura

Junichi Kazama

Masaaki Hama

Tadashi Nota

Yuko Ishibashi

Tomohide Hasegawa

Kenji Masuda

Kozi Miyazima

Yoshimasa Yamamoto

Hirofumi Kinoshita

Shinichi Machida

Yuki Kashiyama

Susumu Kajita

A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.

Memory module having different types of memory mounted together thereon, and information processing device having memory module mounted therein

In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.

DRAM having SDRAM interface and flash memory consolidated memory module

When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.

DRAM with SDRAM interface, and hybrid flash memory module

An OS on a virtual computer at the (n+m)-th stage (n and m represent natural numbers) is caused to recognize a device driver that runs on an OS on the n-th stage virtual computer. Specifically, a shared region is generated in a memory, and the OS at the second stage is caused to recognize, in a pass-through manner, the device driver that runs on the OS at the second stage.

Virtual computer system and I/O implementing method in virtual computer

As regards a hardware fault which has occurred in a computer, a hypervisor notifies an LPAR which can continue execution, of a fault occurrence as a hardware fault for which execution can be continued. Upon receiving the notice, the LPAR notifies the hypervisor that it has executed processing to cope with a fault. The hypervisor provides an interface for acquiring a situation of a notice situation. It is made possible to register and acquire a situation of coping with a hardware fault allowing continuation of execution through the interface, and it is made possible to make a decision as to the situation of coping with a fault in the computers as a whole.

Partial fault processing method in computer system

An information processing apparatus has a task area unit as an area that executes a predetermined process, a power control unit that reads a task area to execute the process from the process and supplies power from a power source to the read task area, and a control unit that executes the process in the task area unit to which the power is supplied by the power control unit.

Information processing apparatus and power saving memory management method with an upper limit of task area units that may be simultaneously powered

When a failure occurs in an LPAR on a physical computer under an SAN environment, a destination LPAR is set in another physical computer to enable migrating of the LPAR and setting change of a security function on the RAID apparatus side is not necessary. When a failure occurs in an LPAR generated on a physical computer under an SAN environment, configuration information including a unique ID (WWN) of the LPAR where the failure occurs is read, a destination LPAR is generated on another physical computer, and the read configuration information of the LPAR is set to the destination LPAR, thereby enabling migrating of the LPAR when the failure occurs, under the control of a management server.

Virtual computer system and control method thereof

A virtual machine system in which a physical CPU busy ratio can be measured in consideration of the status of an assignment of the physical CPU, and the measured CPU busy ratio can be reflected to a CPU busy ratio of each guest OS. An elapsed time counter is provided in a hypervisor, and a hypervisor access interface is provided in each of LPARs and used to read the elapsed time counter from the guest OS. A performance monitor program running on each guest OS calculates, based on a value of the elapsed time counter, the number of sampling timings expected to occur during the time when the physical CPU is not assigned to the LPAR in which the performance monitor program is provided.

Measuring CPU busy ratio and idle time of multiple LPARS by calculating the difference between consecutively acquired elapsed time counter in the virtual machine system

In investigating the cause of a fault in a computer storage system, it is considered useful to previously prepare maintenance logical units (LUs) of a simple structure, the operation of which has been confirmed. If the same number of LUs as servers are prepared for each server as in the prior art, the efficiency is low. Furthermore, securing these LUs complicates assignment of the LUs for construction of a system and a work for addressing the fault. The present invention provides a computer system free of these problems. The computer system has a first computer for executing a first OS (operating system), a second computer for executing a second OS, and a storage array system. The storage array system uses a disk device having a logical unit (LU) for storing a boot loader, as well as the first and second OSes. The boot loader is executed on any one of the two computers, reads in any of the OSes corresponding to the currently operating computer into this operating computer, and executes the read OS.

Computer system for booting a diskless server after a fault by reading a boot loader from a maintenance logical unit and identifying a boot file based on identifier of diskless server

A fault recovering method for substituting an instruction processor (IP) for a system supporting processor to execute processing thereof when the system supporting processor fails. An apparatus implementing this processing method comprises a plurality of processors, at least one of which is operated as a system supporting processor (SSP) and the rest of which are operated as instruction processors. When the SSP fails, an interrupt is generated to an OS running on at least one IP. The OS recognizes that a fault occurred in the IP, abnormally terminates an application program which has been running on the IP when the interrupt was generated, or stops instruction processing as the IP falling into a hardware failure state, or input a command for disconnecting an alternate instruction processor for the system supporting processor, so that the IP takes over functions of the SSP.

Processor fault recovering method for information processing system

In a distributed computer system including a plurality of computers connected to each other via a communication path in which each computer executes processing by use of resources of the other, there is generated schedule information defining a schedule of transferring a status of each computer from one status to another status so as to achieve automatic operation of the computer according to the generated schedule information. One of the computers is used to gather, for each of the computers for which schedule information is to be generated, information of dependence including description of dependence to be held between the computer and other computers at the status transition. According to the collected information of dependence, there is created a dependent graph representing dependence between the computers for the whole system. Generated from the dependent graph is schedule information for each computer. The schedule information is distributed to the computer such that the status thereof is changed according to the distributed schedule information.

Distributed computer system and method of generating automatic operation

A service utilization information collection apparatus in a system including a plurality of computers interconnected through a network acquires names of computers which utilize services provided by a server machine and service utilization status from any one of the computers in the system, and includes a user command which may be executed in any one of the computers, and a service monitor and a local service monitor. A service to be monitored and a name of the server which provides the service are inputted to the user command which is sent to the service monitor. The service monitor issues a service utilization information collection request to the local service monitor operating on each of the computers. The service utilization information collected by the local service monitor is sent to the user through the service monitor and the user command.

Method and apparatus for controlling the shutdown of computer systems by

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Atsugi, Japan

Hitoshi Ueno