Mitsubishi Electric Corporation

Hitoshi Uemura

Yukimasa Hayashida

Daisuke Oya

Yasuhiro Sakai

Ryutaro Date

Ryo Tsuda

Kenji Hatori

Shinichi Iura

Atsushi Narazaki

Yoshiaki Hisamoto

Shota Saito

A semiconductor device includes self-arc-extinguishing elements and a clamp circuit. Each of the self-arc-extinguishing elements has a control terminal and main electrode terminals. The clamp circuit clamps, at the time of turnoff of one of the self-arc-extinguishing elements, the voltage between the main electrode terminals of the self-arc-extinguishing element at a clamp voltage set equal to or lower than 70% of a static withstand voltage that the self-arc-extinguishing element has. The self-arc-extinguishing elements are connected in series with each other. The clamp circuit may be provided between the control terminal and the main electrode terminal of the self-arc-extinguishing elements. The clamp circuit may include a circuit formed by connecting Zener diodes in series such that an anode of one of the Zener diodes is connected to a cathode of another Zener diode.

Semiconductor device

Power semiconductor device

A switching element (A) is connected in parallel to a load (L). A switching element (B) is connected between the switching element (A) and a grounding point. The drive circuit () drives the switching element (A). The drive circuit () drives the switching element (B). Upon detecting a load short circuit, a load short circuit detection circuit () outputs a first signal. A timer () outputs a second signal after a lapse of a predetermined time after inputting the first signal. Upon receiving the first signal, the drive circuit () turns ON the switching element (A). Upon receiving the second signal, the drive circuit () turns OFF the switching element (B).

Semiconductor switching device

A power semiconductor device of the present invention has an active region and an electric field reduction region and includes: an emitter region of a first conductivity type; a base region of a second conductivity type in contact with the emitter region; an electrical strength providing region of the first conductivity type in contact with the base region; a collector region of the second conductivity type in contact with the electrical strength providing region; and a collector electrode in contact with the collector region; wherein the collector region is disposed on both a active region and a electric field reduction region each containing a dopant of the second conductivity type, and the collector region disposed on the electric field reduction region includes a region having a lower density of carriers of the second conductivity type than the collector region disposed on the active region.

Power semiconductor device having an active region and an electric field reduction region

A carrier is prevented from being stored in a guard ring region in a semiconductor device. The semiconductor device has an IGBT cell including a base region and an emitter region formed in an n&#x2212; type drift layer, and a p type collector layer arranged under the drift layer with a buffer layer interposed therebetween. A guard ring region having a guard ring is arranged around the IGBT cell. A lower surface of the guard ring region has a mesa structure provided by removing the collector layer.

A semiconductor device includes a power semiconductor array including a first power semiconductor located on one end of the power semiconductor array, a second power semiconductor located on the other end and a third power semiconductor located between the first and second power semiconductors and a diode array including a first diode located on one end of the diode array, a second diode located on the other end and a third diode located between the first and second diodes. A resistance value between an emitter electrode and a collector electrode in ON state is higher at the third power semiconductor than at the first and second power semiconductors. Upon application of a voltage of not less than a rising voltage, the third diode has a higher resistance value than resistance values of the first diode and the second diode upon application of a voltage not less than a rising voltage.

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Tokyo, Japan

Hitoshi Uemura