Nec Corporation

Pigeon Corporation

Hitoshi Takagi

Jun Yokoyama

Ryotaro Sato

Emi Kuramoto

Muneharu Miyazaki

To ensure the electricity storage amount of a power storage device in preparation for the peak period of power consumption when supplying power to a plurality of devices, a power management apparatus includes a controller that controls the plurality of devices that receive a distribution of total power supplied from the power storage device and another power supply, an acquirer that acquires the remaining electric energy of the power storage device, and a determiner that determines whether the remaining electric energy of the power storage device is not more than a first predetermined value. If the remaining electric energy of the power storage device is not more than the first predetermined value, the controller controls the plurality of devices such that the power from the other power supply is distributed to the power storage device.

Power supply system, power management, apparatus, power management method, and power management program

Power supply system, power management apparatus, power management method, and power management program

This invention provides a server system in which a plurality of servers are divided into a plurality of groups in accordance with a physical arrangement. The server system includes at least one system power provider that distributes and provides system power to each of the plurality of groups, a battery that corresponds to each of the plurality of groups and provides stored power to at least two servers included in the group, and a controller that controls each of the servers included in one group based on power providable by the system power provider and the battery.

Controlling power allocation in a server system that utilizes supplemental batteries

An information processing apparatus includes a hardware processor and a memory storing executable instructions that, when executed by the processor, cause the processor to extract a command from a command cache, complete a process by the command utilizing a predetermined method, input information, which indicates a final result of the process, onto a writing stage when the process by the command has been completed, compute, when operation of information input onto an execution stage for execution of the process by the command has been completed, power consumption required to execute the command stored in the execution stage in accordance with a status of a CPU (central processing unit) or a status of pertained parts around the CPU, and add, when operation of information input onto the writing stage has been completed, the computed power consumption to a current value of a power accumulating register that is a software visible register, so as to obtain accumulated power consumption.

Information processing apparatus that computes power consumption for CPU command

The Thread Data Baseholds a thread identifier to uniquely identify a thread in the system. The Check meanslets, when no thread being a target exist in the same processor, a trap (TRAP)occur. The Issue means, when a thread being a target exists in the same processor, at a time of issuing a subsequent instruction, successively inputs a threadto be executed next, as a thread serving as a target, into a pipeline. The Gate (G) meansuses data on the execution of a thread as an input for computation of a thread serving as a succeeding target. The Switch meanstransfers data in a context of a thread to a context of a target thread without inputting the target thread as a non-executable thread into a pipeline while the thread is being executed.

Multithread processor and method of synchronization operations among threads to be used in same

The drinking cup for learning which can train babies in the drinking movement step-by-step in order to provide a baby, who is at the age of taking milk and taking the liquid food, the lessons of the technique for taking either liquids or the liquid food naturally without spilling them. The drinking cup for learning includes a main container for containing liquid, the main container having at least a cup-shaped opening and a drinking spout member removably attached to the main container. The drinking spout member includes an opening communicating with the main container and a top-opened guide means provided with barrier portions forming at least both side edges.

Drinking learning cup

A multi-processor computer system includes a plurality of computing cells, each of which include a processor, a memory and an interface unit. An interconnect device connects the computing cells. Each of the computing cells are provided with a network driver for the interconnect device so that the computing cells can communicate with each other by using a network protocol.

Multiprocessor system that communicates through an internal bus using a network protocol

Straw cup

An information processing system has a main memory unit, an expanded memory unit, and an instruction processing unit producing a virtual address. An address translation table, namely, a page table stores page table words which include main/expanded memory presence bits indicating to which memory unit of the main memory unit and the expanded memory unit real pages are stored. Preferably, the instruction processing unit may include an access type determiner for determining an access type for at least one operand. The access type indicates which memory unit is the optimum one for the operand. Instead of the access type determiner, the instruction processing unit may include segment descriptor registers for storing segment descriptors having expanded memory bits indicating which memory units are the optimum ones for the segments. In place of the access type determiner, the instruction processing unit may include virtual space registers for indicating virtual space numbers identifying a plurality of virtual spaces and an access type determining circuit for determining which memory unit is the optimum one for a designated virtual space.

Information processing system having an address translation table loaded

The input/output interruption control system comprises a plurality of instruction processors, a plurality of virtual machines, a control program for activation and control of the virtual machines, an input/output processor which activates input/output operation, and a memory (4) for interruption information storing. The instruction processor further comprises registers (53, 63) to store identifiers to identify the virtual machine currently in operation, an interruption acceptance (52, 62) to accept input/output completion interruption requests for the virtual machine currently in operation, and an interruption check (54, 64) which recognizes the existence of an input/output completion interruption request for the virtual machine in operation and activates the input/output completion interruption processing, and a notification bus (5) to send the input/output completion interruption request and the identifier of the specific virtual machine to other instruction processor when the specific virtual machine is activated. Such interruption acceptance (52, 62) of the instruction processors further comprises a input (90) to forcibly activate the interruption check (54, 64) means upon acceptance of an input/output completion interruption and identifier for the specific virtual machine from other instruction processor.

Input/output interruption control system for a virtual machine

A technique for handling an interrupt request issued from an I/O (Input/Output) device controller in a data processing system which is operative in a virtual machine mode in which two flags are provided, the first one of which is set to an 'on' state in the case where a CPU (Central Processing Unit) is utilized as a master unit and is set to 'off' state in the case where the CPU is utilized as a slave unit. The second flag is set to an 'on' state in the case where the CPU is utilized as the master unit and is able to accept the interrupt request directed to a guest OS (Operating System). A first logic gate is arranged to issue a logical product of the output of the first flag and one of the outputs of the I/O device controller. A second logic gate is provided to issue a logical product of the output of the second flag and another of the outputs of the I/O device controller. Further, a third logic gate is arranged to issue a logical sum of the outputs of the first and second gates. An interrupt activator is responsive to the output of the third logic gate and then checks to see if the interrupt request issued from the I/O device controller is acceptable.

Arrangement and a method for handling interrupt requests in a data

In an address translation device (11) used in combination with a main memory (12) in translating an input virtual address into an output real address, an address translation buffer (15) is for memorizing not only a plurality of buffer virtual addresses (BVA) and a plurality of buffer real addresses (BRA) corresponding to respective buffer virtual addresses but also buffer presence bits (BP) corresponding to respective buffer real addresses to indicate presence or absence of a datum of a memory real address in the main memory in correspondence to each of the buffer real addresses. A comparison control circuit (17) compares the input virtual address with a particular one of the buffer virtual addresses, that corresponds to the input virtual address to make the address translation buffer produce, as the output real address, a particular one of the buffer real addresses, which corresponds to the particular buffer virtual address when the input virtual address coincides with the particular buffer virtual address.

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Tokyo, Japan

Hitoshi Takagi