Canon Kabushiki Kaisha

Fujitsu Corporation

Renesas Electronics Corporation

Tdk Corporation

Sony Corporation

Other

Calsonic Kansei Corporation

Kabushiki Kaisha Toshiba

Hitachi, Ltd.

Nec Corporation

Olympus Medical Systems Corporation

Kabushiki Kaisha Topcon

Nihon Kohden Corporation

Eagle Industry Co., Ltd.

Seiko Instruments & Electronics Ltd.

Hitoshi Suzuki

Naoyuki Yamamoto

Takahiro Nakase

Yasuhiro Yoshimura

Yasuo Nami

Toshihiko Miyajima

Nobuo Kamehara

Koichi Niwa

Koji Adachi

Tokihiko Ogura

Takeshi Yamamoto

Hiroshi Igarashi

Susumu Saito

Shinya Watanabe

Kazunori Yamanaka

Toru Tojo

Ryoichi Hirano

Takuya Uzumaki

Kenichi Inoue

Kazuo Abe

Takashi Nakagawa

Tomio Iwasaki

Takeshi Ogasawara

Hiromichi Yamada

Kenji Kojima

Hiromitsu Yokoyama

Yoshihiko Imanaka

Mineharu Tsukada

Teppei Hirotsu

Takuya Aoyagi

Mitsuo Yamashita

Tsutomu Okabe

Akihiko Aoyagi

Kenichiro Abe

Masatoshi Tanaka

Hideaki Yoshimura

Kenji Fukuzono

Takashi Kanda

Kenji Iida

Yusuke Abe

Toshiharu Kondo

Rika Ono

Hirotaka Motai

Kei Fukui

Kazuya Arai

Yasuhiro Tawara

Shinpei Ikegami

Mutsuo Sasaki

Yukihiko Akaike

Takashi Uchida

Takato Machi

Kohtaroh Higuchi

Yasuhito Takahashi

Koji Omote

Hideyuki Nishida

Kaoru Hashimoto

Toshio Ohashi

Wataru Yamagishi

Toshiharu Watanabe

Hiroshi Kanemoto

Hiroaki Date

Toru Sato

Yasutomo Maehara

Takeshi Satoh

Joji Nagahira

Yoichi Yuyama

Tomohiro Ono

Kichinosuke Hirokawa

Takeshi Kamisaku

Yukio Miyazaki

Masahide Nagai

Tomohisa Yagi

Ryota Okazaki

Akihiro Yamate

Hiromi Ogawa

Shuji Satoh

Kaoru Sugimoto

Toshikazu Yoshihara

Kazuhiko Otake

Koichi Shiga

Takeshi Kagaya

Naoto Okazaki

Manabu Uomoto

Minoru Noda

Hidehiko Fujisaki

Masato Ohno

Toshinori Kawamura

Haruhiro Osada

Koichiro Oikawa

Seiichi Sugano

Masashi Takada

Takayuki Nishijima

Norio Fueki

Nobuhide Okada

Emiko Ouchi

Chieko Watanabe

Tsuyoshi Nagao

Keitaro Nakamura

Yuuji Ohtsuka

Yuuya Toe

The preset invention has as its object the provision of a laminate free of hexavalent chromium and excellent in corrosion resistance and wear resistance, and a manufacturing process of the laminate. To solve the above-described problems, a laminate according to the present invention includes a substrate, and a laminated film portion with metal films laminated in two or more layers. The laminate has an interface layer between each two adjacent ones of the metal films. The laminated film portion contains a first metal element as a principal component, the first metal element being at least one element of Ni, Cr, Co, and W, and a second metal element that is a metal element of smaller cohesive energy than that of the first metal element. The second metal element contained in the interface layer is at a content ratio higher than that of the second metal element contained in each of the adjacent metal films.

Laminate, metal plating solution, and manufacturing process of laminate

A conveyance apparatus includes a stator including a plurality of coils arranged along a first direction and a mover. The mover moves along the plurality of coils and includes a first magnet group including a plurality of first magnets arranged to face the plurality of coils along the first direction, and a second magnet group including a plurality of second magnets arranged to face the plurality of coils along a second direction intersecting with the first direction. At least one of the plurality of coils includes a core, a wire-wound portion wound around the core, and a yoke. The yoke is adjacent to an outer periphery of a portion of the wire-wound portion along the first direction and extends in the first direction.

Conveyance apparatus and method of manufacturing article

In a transport system that moves a moving portion, which moves in a transport direction along a fixed portion, while detecting a position of the moving portion by a scale and a sensor, a guide block is installed on a second surface of a first part of the moving portion, a guide rail is installed on a first surface of the fixed portion, the scale is installed at an end of the first part of the moving portion on an opposite side across the guide block, and a sensor that has a detecting unit at a position facing the scale is installed in the fixed portion.

Transport system, processing system, and article manufacturing method

To provide new instruction and device suitable for tracing execution of a computer program. In an embodiment, a CPU is configured so as to supply a constant to a trace unit in response to decoding of a first instruction having an immediate field indicating the constant. In addition, the trace unit is configured so as to output trace data including the constant in response to execution of the first instruction in the CPU.

Computer and compiling method

A computer system includes a first bus, a second bus, and a third bus, a first bus bridge that is disposed between the first bus and the second bus, and detects a bus error on the second bus, a second bus bridge that is disposed between the second bus and the third bus, and detects a bus error on the third bus, a first device coupled to the second bus, a second device coupled to the third bus, an interrupt controller that notifies a bus error in accordance with the detection of the bus error, and a multi-thread processor. The multi-thread processor includes a schedule register that stores an execution order and data for a plurality of virtual CPUs, and a virtual CPU execution circuit that executes the virtual CPUs in accordance with the execution order.

Computer system

A mechanical seal device for use in a water environment includes: a stationary sealing ring made of SiC; and a rotating sealing ring made of SiC and arranged opposite to the stationary sealing ring, the mechanical seal device bringing opposite sliding surfaces of the stationary sealing ring and the rotating sealing ring into close contact with each other to seal a sealed fluid, wherein at least one of the sealing rings including the sliding surfaces is configured by a sintered compact of a material including SiC as a base material compounded with an Al additive, and a specific resistance value of the sealing ring configured by the sintered compact including the sliding surface is equal to or lower than 100 &#x3a9;&#xb7;cm.

Mechanical seal device for use in water environment and sealing ring thereof

In a system for performing clock generation for each semiconductor device, synchronization between the semiconductor devices is achieved without causing a count value in a counter to be discontinuously changed. A semiconductor deviceincludes a clock oscillator, a counterconfigured to count the number of clocks, a periodic registerin which a value corresponding to a period for synchronization is set, a comparison circuitconfigured to compare the count value in the counterwith the set value in the periodic register, a match flag registerin which a predetermined value is set when the count value coincides with the set value, a match output terminalconfigured to output the value in the match flag registerfrom the own semiconductor device, a match input terminalto which a value output from another semiconductor device to be synchronized is input, and a reset circuit configured to reset the counterand the match flag registerwhen both the value in the match flag registerof the own semiconductor device and the value input to the match input terminalbecome a predetermined value.

Semiconductor device, control system, and synchronization method

A memory control system includes a memory connected to a memory bus, the memory including a plurality of access areas, a memory controller connected to the memory bus, a plurality of registers corresponding to the plurality of access areas, each of the plurality of registers configured to set an access permission or prohibition for a corresponding access area, a CPU (Central Processing Unit) configured to issue a first access request for accessing one of the plurality of access areas, and a memory access controller configured to determine whether an access to the memory is permissible or prohibited using the first access request and the plurality of registers, the memory access controller outputting a second access request in accordance with a determination result.

Microcomputer and method for controlling memory access

A data processing apparatus includes an instruction execution section, a protection control information storage section that stores protection control information that includes first protection information, and second protection information that is independent of the first protection information, an instruction protection information storage section that stores instruction protection information for specifying a partial address space of an instruction address space in which to store instructions that are executable by the instruction execution section, a data protection information storage section that stores data protection information for specifying partial address spaces of a data address space in which to store operands to be usable by the instruction execution section, and a protection violation determination section which, when the first protection information includes a first value, makes a determination as to whether to permit the instruction execution section to access the instruction address space according to the instruction protection information.

Data processing apparatus and address space protection method

A computer system includes an interrupt controller to notify a bus error occurrence, and a multithreaded processor. The multithreaded processor includes a schedule register that settles a sequence of performing a plurality of virtual CPUs and stores data for virtual CPUs to be performed, and a virtual CPU execution portion that performs virtual CPUs according to a sequence settled by the schedule register. Virtual CPUs operate different operating systems (OS's) and include a first virtual CPU that operates a management OS to manage other OS's. When notified of bus error occurrence, the virtual CPU execution portion operates only the first virtual CPU regardless of an execution sequence settled in the schedule register. The first virtual CPU reinitializes a bus where an error occurred.

A method of manufacturing a circuit board includes forming a first electrode on a support substrate, covering the support substrate and the first electrode with a first insulating layer, polishing the first insulating layer to expose a first surface of the first electrode, forming a first wiring on the first insulating layer after exposing the first surface of the first electrode, the first wiring being connected to the first electrode, and removing the support substrate to expose a second surface of the first electrode after forming the first wiring.

Method of manufacturing circuit board, method of manufacturing electronic device, and electronic device

A grip apparatus includes a robot hand including plural fingers and pressure sensitive conductive rubber provided to the finger and configured to output a detection signal equivalent to acting force. The pressure sensitive conductive rubber is covered by a cover member. The grip apparatus also includes a control unit configured to cause the plural fingers to perform an opening or closing operation and compare a detection value based on the detection signal from the pressure sensitive conductive rubber with a threshold to determine whether the robot hand grips the work or releases the work. During a period from a time when the closing operation is started until a time when the fingers contacts the work, the control unit samples the detection signal of the pressure sensitive conductive rubber and sets the threshold as a value higher than a detection value at a time of this sampling.

Grip apparatus, control method for the grip apparatus, and robot manipulator

A microcomputer including a CPU, a plurality of protection information storages configured to store memory protection information specifying an access permission state or access prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information, and a reset apparatus configured to output a reset signal to the plurality of protection information storages according to a reset request output from the CPU according to a switching of programs executed by the CPU. Each of the plurality of protection information storages is set to a second memory protection state according to the reset signal from a first memory protection state.

A data processing device includes an instruction executing part executing a normal task and a management task scheduling an execution order of the normal task with switching the normal task and the management task, a counter measuring an execution state of the normal task being executed in the instruction executing part, and a state controller controlling the counter based on the normal task being executed in the instruction executing part. The instruction executing part determines whether the normal task to be executed next of a plurality of normal tasks scheduled by the management task is a measurement object or not, and outputs an operation signal notifying the state controller of the determination result. The state controller operates the counter in accordance with the branch operation.

Data processing device and method of controlling the same

There is a need to provide a computer system capable of preventing a failure from propagating and recovering from the failure. VCPU#through VCPU#each operate different OS's. VCPU#operates a management OS that manages the other OS's. When notified of bus error occurrence, a virtual CPU execution portionoperates only VCPU#regardless of an execution sequence stored in schedule register A. VCPU#reinitializes a bus where an error occurred.

Growing community of inventors

Tokyo, Japan

Hitoshi Suzuki