Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Panasonic Holdings Corporation

Tower Semiconductor Ltd.

Hitoshi Suwa

Yasuhiro Tomita

Manabu Komiya

Toshiki Mori

Noam Eshel

Kazuyuki Kouno

Takashi Ono

Masayoshi Nakayama

Reiji Mochida

Yuriko Hayata

Jeffrey Allan Jacob

Yuriko Ishitobi

Tamas Toth

Avi Parvin

Yukimasa Hamamoto

Connection weight coefficients to be used in a neural network computation are stored in a memory array. A word line drive circuit drives a word line corresponding to input data of a neural network. A column selection circuit connects to a computation circuit bit lines to which a connection weight coefficient to be computed is connected. The computation circuit determines the sum of cell currents flowing in the bit lines. A result of the determination made by the computation circuit is stored in an output holding circuit, and is set as an input of a neural network in the next layer, to the word line drive circuit. A control circuit instructs the word line drive circuit and the column selection circuit to select the word line and the bit line to be used in the neural network computation, based on information held in a network configuration information holding circuit.

Neural network computation circuit including semiconductor memory element, and method of operation

A bitwise bidirectionally rewritable nonvolatile semiconductor storage device capable of performing a high-speed data rewrite, while enhancing endurance characteristics and data-retention characteristics of a memory cell. To achieve high-speed generation of rewrite-bit information indicating that a data rewrite is needed or not, the structure employs a logic circuit corresponding to the number of change patterns of write conditions and concurrently compares between read-out data RO of memory at the start of the data rewrite and prepared write data DIN. After an electrical data rewrite of the memory, the data rewrite is verified based on the rewrite-bit information stored in an internal buffer circuit. This protects an already-rewritten memory cell from unnecessary additional rewrite.

Nonvolatile semiconductor storage device and rewriting method thereof

A semiconductor leakage current detector of the present invention includes a first analog switch which causes a current to be measured to flow or to be cut off, a second analog switch which causes a reference current to flow or to be cut off, an integral capacitance element which is connected by the first analog switch and the second analog switch and is charged with the current to be measured or the reference current, a discharge unit which discharges the integral capacitor, and a comparison unit which compares the reference voltage with each of an integral voltage generated in the integral capacitor by a reference current after the discharge of the integral capacitor and an integral voltage generated in the integral capacitance element by the current to be measured after the discharge of the integral capacitor.

Semiconductor leakage current detector and leakage current measurement method, semiconductor leakage current detector with voltage trimming function and reference voltage trimming method, and semiconductor integrated circuit thereof

In conventional memory arrays in which a bit line is shared by memory cells, a cell current flows over into neighbor cell(s) in a program verify process, and therefore, the threshold of a memory cell to be programmed is erroneously determined to be lower. Therefore, in a program verify process, a control circuitwrites a fail value to a neighbor cell bufferwhen all neighbor cell(s) having an offset of n or less from a memory cell to be programmed are in the erased state, and when otherwise, writes a pass value to the neighbor cell buffer. The control circuitverifies input write data and also verifies data stored in the neighbor cell buffer(s). In the latter verify process, a verify voltage higher than an ordinary one is used to compensate for the leakage of cell current.

Flash memory and program verify method for flash memory

The non-volatile semiconductor storage deviceincludes the specific command Enable/Disable signal linesconnected to the command decoder. The specific command Enable/Disable signals are externally inputted to the command decoderthrough the signal lines. Thereby, when the deviceis initialized, the command decoderenables the specific command and the devicecan shift to a mode corresponding to the specific command. On the other hand, the command decoder 108 can disable the specific command, for example, when a user uses the device, thereby preventing the specific command from being executed even when the specific command is erroneously issued.

Non-volatile semiconductor storage device with specific command enable/disable control signal

An n-bit status signal indicating an execution state of a write command is outputted from a status register. At the time of data writing, an output switching circuit outputs (n&#xd7;m)-bit data in which a status signal pattern repeats m times. At the time of data reading, the output switching circuit outputs data stored in a memory cell array.

Nonvolatile semiconductor memory device for outputting a status signal having an output data width wider than an input data width

Each boosting cell includes: a first n-transistor having a diode connection; a second n-transistor whose gate and drain are connected to a power supply voltage and whose source is connected to the source of the first n-transistor; and a boosting capacitor provided between the drain of the first n-transistor and a boosting clock input terminal to which a clock signal is input. The boosting capacitor is connected to n auxiliary boosting capacitors in parallel via connection switching circuits controlled with boosting ability switching signals as control signals input from the outside.

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Osaka, Japan

Hitoshi Suwa