Fuji Electric Co., Ltd.

Sharp Kabushiki Kaisha Corporation

Honda Motor Co., Ltd.

Fuji Electric Systems Co. Ltd.

Kyushu University

Hitoshi Sumida

Masaharu Yamaji

Hiroshi Kanno

Akinobu Teramoto

Masaru Saito

Taichi Karino

Ken-ichi Nonaka

Osamu Sasaki

Toshio Naka

Masashi Akahane

Takeyoshi Nishimura

Yoshiaki Toyoda

Akihiro Jonishi

Akihiko Ohi

Hiroyuki Tanaka

Rongxiang Wu

Kin-On Sin

Chun-Wai Ng

Yoshiaki Toyada

Lulu Peng

Masahiro Sasaki

Akira Nakamori

Takahiro Mori

Johnny Kin On Sin

Kazumi Takagiwa

Hideto Kobayashi

Hiroshi Shimabukuro

Hiroshi Nakashima

Johnny Kin-On Sin

Wataru Tomita

Haigui Yang

Hideaki Itoh

Koji Ikegami

A semiconductor device includes: a wiring layer; a titanium nitride layer deposited on the wiring layer; a titanium oxynitride layer deposited on the titanium nitride layer; a titanium oxide layer deposited on the titanium oxynitride layer; and a surface passivation film deposited on the titanium oxide layer, wherein an opening penetrating the titanium nitride layer, the titanium oxynitride layer, the titanium oxide layer, and the surface passivation film is provided to expose a part of the wiring layer so as to serve as a pad.

Semiconductor device and method of manufacturing the same

A semiconductor device includes: a semiconductor layer of a first conductivity-type; a well region of a second conductivity-type provided at an upper part of the semiconductor layer; a base region of the second conductivity-type provided at an upper part of the well region; a carrier supply region of the first conductivity-type provided at an upper part of the base region; a drift region of the first conductivity-type provided separately from the base region; a carrier reception region of the first conductivity-type provided at an upper part of the drift region; a gate electrode provided on a top surface of the well region interposed between the base region and the drift region via a gate insulating film; and a punch-through prevention region of the second conductivity-type provided at the upper part of the well region and having an impurity concentration different from the impurity concentration of the base region.

A method of manufacturing a semiconductor integrated circuit includes a first ion implantation process implanting impurity ions of a second conductivity type into a bottom surface of a semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a first current suppression layer, and a second ion implantation process implanting impurity ions of a first conductivity type into the bottom surface of the semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a second current suppression layer. The semiconductor integrated circuit includes a first well region of the first conductivity type and a second well region of the second conductivity type provided in an upper portion of the first well region. The first current suppression layer is separated from the first well region and the second current suppression layer is provided under the first current suppression layer.

Method of manufacturing semiconductor integrated circuit

Provided is a resistance element, including: a semiconductor substrate; a first insulating film stacked on the semiconductor substrate; a resistance layer selectively stacked on the first insulating film; a first auxiliary film separated from the resistance layer; a second auxiliary film separated from the resistance layer in a direction different from that of the first auxiliary film; a second insulating film stacked on the first insulating film to cover the resistance layer, and the first auxiliary film and the second auxiliary film; a first electrode connected to the resistance layer and stacked on the second insulating film disposed on an upper side of the first auxiliary film; and a second electrode connected to the resistance layer by being separated from the first electrode and stacked on the second insulating film on the upper side of the second auxiliary film.

Resistance element and manufacturing method of resistance element

A semiconductor integrated circuit includes: a first well region of a first conductivity type; a second well region of a second conductivity type provided in an upper portion of the first well region; a first current suppression layer of a second conductivity type being provided to be separated from the first well region in a lower portion of a base-body of the second conductivity type directly under the first well region and having an impurity concentration higher than that of the base-body; and a second current suppression layer of the first conductivity type provided under the first current suppression layer so as to be exposed from a bottom surface of the base-body.

Semiconductor integrated circuit

A resistive element includes: a semiconductor substrate; a first insulating film deposited on the semiconductor substrate; a resistive layer deposited on the first insulating film; a second insulating film deposited to cover the first insulating film and the resistive layer; a first electrode deposited on the second insulating film and electrically connected to the resistive layer; a relay wire deposited on the second insulating film without being in contact with the first electrode, and including a resistive-layer connection terminal electrically connected to the resistive layer and a substrate connection terminal connected to the semiconductor substrate with an ohmic contact; and a second electrode deposited on a bottom side of the semiconductor substrate, wherein a resistor is provided between the first electrode and the second electrode.

Resistive element and method of manufacturing the resistive element

To provide a semiconductor integrated device capable of a gate screening test with no need for any additional circuit and without adding any gate screening terminal. The semiconductor integrated device includes a gate drive unit configured to drive the gate of a voltage controlled semiconductor element and a regulator configured to supply a gate drive voltage to the gate drive unit. The regulator includes an external connection terminal capable of receiving a gate screening voltage for the voltage controlled semiconductor element in a gate screening test.

Semiconductor integrated device and gate screening test method of the same

A semiconductor integrated circuit includes a semiconductor layer of a first conductivity type which is stacked on a support substrate with an insulating layer interposed between the semiconductor layer and the support substrate, a first well region of a second conductivity type buried in an upper part of the semiconductor layer so as to be separated from the insulating layer, a second well region of the first conductivity type buried in an upper part of the first well region, and an isolation region of the first conductivity type buried in the upper part of the semiconductor layer such that the isolation region surrounds the first well region and is separated from the first well region and the insulating layer.

A method of manufacturing a semiconductor device according to the invention includes the step Sof cleaning the silicon carbide substratesurface, the step Sof bringing a material gas into a plasma and irradiating the atoms contained in the material gas to silicon carbide substratefor growing silicon nitride filmon silicon carbide substrate, the step Sof depositing silicon oxide filmon silicon nitride filmby the ECR plasma CVD method, and the step Sof annealing silicon carbide substrateincluding silicon nitride filmand silicon oxide filmformed thereon in a nitrogen atmosphere. By the method of manufacturing a semiconductor device according to the invention, a semiconductor device that exhibits excellent interface properties including an interface state density and a flat band voltage is obtained.

Method of manufacturing semiconductor device

A semiconductor integrated circuit includes a first well region of a first conductivity type; a second well region of a second conductivity type provided in an upper part of the first well region; a current suppression layer of the first conductivity type provided in a lower part of the semiconductor substrate immediately below the first well region, separated from the first well region; and an isolation region of the second conductivity type provided in an upper part of the semiconductor substrate, separated from the first well region, a reference potential being applied to the isolation region. The semiconductor substrate is the second conductivity type.

A mask used to form an nsource layer () is formed by a nitride film on the surface of a substrate before a trench () is formed. At this time, a sufficient width of the nsource layer () on the surface of the substrate is secured. Thereby, stable contact between the nsource layer () and a source electrode () is obtained. A CVD oxide film () that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode () embedded in the trench (), and non-doped poly-silicon () that is not oxidized is formed on the CVD oxide film (). Thereby, generation of void in the CVD oxide film () is suppressed and, by not oxidizing the non-doped poly-silicon (), a semiconductor apparatus is easily manufactured.

MOS-driven semiconductor device and method for manufacturing MOS-driven semiconductor device

An isolator is configured by a transmission circuit, a transformer, and a reception circuit. A first coil of the transformer is disposed on a back surface of a first semiconductor substrate; a transmission circuit and a second coil of the transformer are disposed on a front surface. The first coil is embedded within a coil trench, is led out through an embedded via-metal-film to a substrate front surface, and is electrically connected to the transmission circuit. The second coil is disposed on an insulating layer of the substrate front surface. The reception circuit is disposed on a front surface of a second semiconductor substrate. The second coil and the reception circuit are electrically connected to each other by connecting first and third electrode pads disposed respectively on the front surfaces of the first and second semiconductor substrates through wires.

Isolator and method of manufacturing isolator

A semiconductor device that has a level shift circuit, an anterior stage circuit, and a posterior stage circuit. The level shift circuit transmits an input signal from a primary potential system to a secondary potential system different from the primary potential system. The anterior stage circuit including a first transistor receives a gate driving signal delivered by the level shift circuit. The posterior stage circuit including a second transistor with the same channel type as that of the first transistor drives a switching element according to the output signal from the first transistor. The threshold voltage of the first transistor is set at a lower value than the threshold voltage of the second transistor.

Semiconductor device and power converter equipment

A semiconductor device is provided with a first well region of a first conduction type having a first voltage (voltage VB) applied thereto, a second well region of a second conduction type formed in the surface layer section of the first well region and having a second voltage (voltage VS) different from the first voltage applied thereto, and a charge extracting region of the first conduction type formed in the surface layer section of the second well region and having the first voltage applied thereto. This inhibits the operation of a parasitic bipolar transistor.

Growing community of inventors

Matsumoto, Japan

Hitoshi Sumida