Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Video and Information System, Inc.

Hitachi Techno Engineering Co., Ltd.

Hitoshi Sadamitsu

Masatsugu Shinozaki

Tetsuya Mochida

Hideki Kamimaki

Kazushi Kobayashi

Kiyokazu Nishioka

Tadashi Kyoda

Hiroshi Ito

Tsuguji Tachiuchi

Shigeo Tsujioka

Takao Ohba

Nobuo Tsuchiya

Katsuya Takanashi

Megumu Kondo

Koichi Isaji

Masahiro Jinushi

Masami Jikihara

Kazuhiko Fukuoka

Takahiro Kawai

Shuji Kamiya

Hironori Uchida

Takashi Yoshitomi

A data processing apparatus which includes a display unit and a power supply controller for supplying power to the display unit. The display unit has a display screen and a back light controller. The power supply controller comprises a switch, at least one output line for receiving the power from the switch and for supplying therethrough the power to electronic devices, a delay circuit for receiving the power from the switch and when the switch is turned ON to start supply of the power, for outputting the power after passage of a predetermined time from the start of the power supply, and a second output line for supplying the power from the delay circuit to the back light controller therethrough. The display unit has a memory means for storing therein a luminance data on the display screen through the back light controller when the power supply is turned OFF and for determining an output state of the display unit through the back light controller on the basis of the luminance data read out from the memory means when the power supply is turned ON. Further, the data processing apparatus has a means for invalidating output of a display data to be output onto the display screen and a means, after the display data is invalidated, for reducing a frequency of a timing signal or invalidating output of the timing signal for the display unit.

Data processing apparatus, power supply controller and display unit

An address bus control system is provided of the type in which a controller including a central processing unit is connected through an address bus and a data bus to hardware modules which control equipment to be controlled. An address space defined by an address bus includes a discrimination space for discriminating the attribute of the hardware module and a function space for allocating and clearing an address space for a function interface of the hardware module. The attribute of a hardware module connected to a connector having a corresponding address is recognized using the discrimination space. The function interface of each hardware module is assigned a space within the function space in accordance with the contents of the discrimination space in concern, or the assigned space is canceled. An address of the function space can be allocated to only a necessary function interface, merely by connecting the hardware module to the connector, allowing to set up hardware modules equal to or larger than the total address space.

Address bus control system

A plurality of process requests generated from processing units, for example, direct memory access (DMA) channels are controlled by a preference circuit in accordance with a priority level assigned to each of the processing unit. An information of the highest priority obtained processing unit and its priority level is stored in latches. Another process requests having the same priority level as the stored processing unit are inhibited from being supplied to the preference circuit, so that the first generated process request is accepted and executed prior to acceptance of the another process requests having the same priority level.

Process request arbitration system which preferentially maintains

In a data processing system having a central processing unit, at least an input/output unit such as an MT unit or a floppy disk unit, a memory, an address bus, a first address translation unit, a second address translation unit, and an address selection unit, an output address from the central processing unit is translated by the first address translation unit to supply a resultant address to the address bus and, an output address from the input/output unit is directly fed to the address bus. An address on the address bus is delivered to the address selection unit, and the address selection unit selectively supplies the memory with the output address delivered from the first translation unit onto the address bus or with the resultant address obtained by translating the output address from the input/output unit by means of the second translation unit. In this configuration, the second address translation unit, to translate an address from the input/output unit, is disposed at an input to the memory, which eliminates the necessity for a translator on the side of the input/output device.

Data processing system employing two address translators, allowing rapid

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Hiratsuka, Japan

Hitoshi Sadamitsu