Mitsubishi Electric Corporation

Mitsubishi Denki Kabushiki Kaisha

Hitoshi Kurusu

Yoshihiro Tsukahara

Hiroyuki Hoshi

Takumi Sugitani

Kazuya Yamamoto

Miyo Miyashita

Yoshinobu Sasaki

Kazuhiro Maeda

Yoshihiro Notani

Tomoyuki Asada

Takayuki Hisaka

Junichi Udomoto

A semiconductor device () according to the present disclosure includes: an n-channel depletion-mode transistor (); an input matching circuit inside which the gate terminal () and the ground terminal () are DC-connected; a self-bias circuit () including a resistor () biasing the transistor () by a voltage drop due to a current flowing through the resistor (), and a capacitor () connected in parallel to the resistor) and regarded as short-circuit at a frequency of the high-frequency power; and a diode () having an endmost anode connected to the source terminal () and an endmost cathode connected to the ground terminal (), and connected in one stage or connected in series in a plurality of stages in the same direction.

Semiconductor device

A multi-finger transistor including plural control electrodes (), plural first electrodes (), and plural second electrodes () is provided on a semiconductor substrate (). A resin film () covers the transistor. A first wiring () electrically connecting the plural first electrodes () to one other is provided on the resin film (). The resin film () covers contact portions between the first wiring () and the plural first electrodes (). A first hollow structure () sealed with the resin film () is provided around the plural control electrodes () and the plural second electrodes ().

Semiconductor device and method for manufacturing same

A current reuse type FET amplifier according to the present invention has a capacitance provided between a drain of a first FET in a first stage and a gate of a second FET in a next stage, electrically separates a gate voltage of the second FET from a drain voltage of the first FET, and includes a control circuit controlling the gate voltage of the first FET and the gate voltage of the second FET so that a variation of a drain current of the second FET and a variation of a drain voltage of the first FET are reduced in accordance with a variation of a saturation current Idss of the FET. Furthermore, the current reuse type FET amplifier according to the present invention uses only a depression mode FET to provide a circuit configuration operable with a positive single power source.

Current reuse type field effect transistor amplifier

According to the present invention, an integrated circuit includes a first amplifier stage, a second amplifier stage, a first signal line connecting an output of the first amplifier stage and an input of the second amplifier stage to each other, a first plane for ground connected to the first amplifier stage, a second plane for ground connected to the second amplifier stage and at least one at least one line for ground connecting the first plane and the second plane to each other, wherein the at least one line has a center line having a length of 10 &#x3bc;m to 1 mm, a width of the at least one line is &#x2153; or less of a width of the first plane, and a pattern ratio is 1 or more.

Integrated circuit

A frequency includes an input terminal, an output terminal, a transistor having a gate terminal which receives input of a signal including a first frequency from the input terminal, a source terminal and a drain terminal connected to the output terminal by a main line, an output matching circuit provided in the main line, the output matching circuit shutting off the first frequency while allowing an output frequency multiplied from the first frequency to pass therethrough, a branch line including a power supply terminal for connection to a power supply, the branch line branching off from a branch point in the main line, and a first diode provided in the branch line, the first diode having an anode connected to the power supply terminal and a cathode connected on the branch point side.

Frequency multiplier

A frequency multiplier includes an input terminal, an output terminal, a first transistor having a first gate to which a radiofrequency signal is input from the input terminal, a first drain from which an output signal is issued to the output terminal, and a first source, a second transistor having a second gate, a second source to which the radiofrequency signal is input from the input terminal, and a second drain from which an output signal is issued to the output terminal, and a stabilizing resistor which is a resistor connected to the second gate, wherein no resistor exists on the path for the radiofrequency signal, and wherein the stabilizing resistor suppresses a reflex gain produced by the second transistor.

A transistor includes: a semiconductor substrate; a first electrode on the semiconductor substrate and having first and second portions; a second electrode on the semiconductor substrate and spaced apart from the first electrode; a control electrode on the semiconductor substrate and disposed between the first electrode and the second electrode; and a first heat sink plate joined to the second portion of the first electrode without being joined to the first portion of the first electrode.

Transistor with heat sink joined to only part of one electrode

A directional coupler includes capacitive elements electrically connected to a coupled port and an isolated port, respectively, for a coupled line on a chip (on-chip). The capacitive elements serve as matching capacitive elements and may be MIM (Metal Insulator Metal) capacitors on a substrate. A first end of a first of the capacitive elements is connected between the coupled port and the coupled line and a second end is grounded. A first end of a second of the capacitive elements is connected between the isolated port and the coupled line and a second end is grounded.

Directional coupler

A method for inspecting a semiconductor device includes establishing a first circuit state in which electrical conduction through at least one of branch transmission line portions is established and electrical conduction through at least one other branch transmission line portion is prevented. Then, electrical signal reflection characteristics of the transmission line are measured. The method also includes establishing a second circuit state in which electrical conduction through the at least one of the branch transmission line portions is prevented and electrical conduction through the at least one other branch transmission line portions is established. Then, the electrical signal reflection characteristics of the transmission line are measured. The second circuit state is a mirror image of the first circuit state with respect to the primary transmission line. The measured values are compared.

Method for inspecting transmission line characteristic of a semiconductor device using signal reflection measurement

In a high frequency circuit property measurement method, prior to property measurements of a high frequency circuit with RF measurement probe heads, RF measurement probe heads are calibrated using a calibration pattern comprising a signal line having a characteristic impedance and extending on a dielectric substrate, a first GND pad having one end disposed close to and at an interval from a first end of the signal line, a second GND pad having one end disposed close to and at an interval from a second end of the signal line, and a conductor electrically coupling the first GND pad to the second GND pad.

Circuit property measurement method

A semiconductor integrated circuit device and a printed wired board which self-align to each other in an exact and precise manner. The semiconductor integrated circuit device has conductive bumps. The printed wired board has conductive recessed members at positions corresponding to the conductive bumps. Each of the conductive bumps is fitted into the corresponding conductive recessed member so that the printed wired board is aligned with the semiconductor integrated circuit device.

Semiconductor integrated circuit device and printed wired board for mounting the same

A field effect transistor (FET) having a stabilization circuit with a stabilization condition not affected by another circuit element, for example, a matching circuit. The stabilization circuit is pre-formed inside of the FET, thereby pre-stabilizing the FET in a frequency range in which a power amplifier is used.

Field effect transistor including stabilizing circuit

A semiconductor device with a field-effect transistor for use at a high frequency, higher than the microwave frequency band, has a pair of grounding electrodes, each having a via hole with an elliptical cross-section, the major axis of which is parallel to a direction in which source electrodes are arranged. Instead of the elliptical via hole, each grounding electrode may have via holes through which the grounding electrode is grounded.

Field effect transistor with comb electrodes and via holes

In a power amplifier including an input matching circuit; an output matching circuit; and first and second transistors receiving a gate bias and a drain bias, the transistors having the same pinch-off voltage and being connected in parallel; resistors connected to the gates of the transistors, grounding the gate of the transistors. The resistances of the resistors are set so that when the output power increases proportionally to the input power, a gate bias applied to the first transistor exceeds the pinch-off voltage to the first transistor is ON white the gate bias applied to the second transistor does not exceed the pinch-off voltage and is OFF, and when the output power does not increase proportionally to the input power, the gate bias applied to the second transistor exceeds the pinch-off voltage of the second transistor so that both of the first and second transistors are ON. The power amplifier produces constant output power levels with respect to a wide range of input power levels.

Growing community of inventors

Tokyo, Japan

Hitoshi Kurusu