Nec Corporation

Hitoshi Kurosaka

Naotaka Maeda

Hideyuki Emura

The present invention is used to verify an equivalence between a software for realizing a predetermined function and a hardware data created according to the software and constituting a hardware operating identically as a processing by the software. The LSI verification method of the present invention simulates each of the hardware data and the software and compares, according to a signal I/O condition defining operation of the hardware, an I/O signal state as a simulation result by the hardware data to a software variable as a simulation result of the software for verification of the equivalent.

LSI verification method, LSI verification apparatus, and recording medium

A logic circuit verification device comprising a data input section to read the circuit data and the circuit information of the logic circuits to be verified and converts them into the intermediate format, a corresponding point detection section to extract and output the information about the corresponding points using the corresponding point detection algorithm, a circuit partitioning section to read the intermediate format data and partition the logic circuits according to the corresponding point information obtained by the corresponding point detection section so as to prepare circuit data of the subcircuits and a equivalence checking section to read the circuit data of the subcircuits, determine the subcircuits to be compared with referring to the corresponding point information obtained by the corresponding point detection section and comparatively compares the circuit data of the subcircuits.

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Tokyo, Japan

Hitoshi Kurosaka