Semiconductor Energy Laboratory Co., Ltd.

Hitoshi Kunitake

Shunpei Yamazaki

Takayuki Ikeda

Hajime Kimura

Kazuki Tsuda

Tatsuya Onuki

Yuto Yakubo

Tomoaki Atsumi

Kiyoshi Kato

Kazuaki Ohshima

Hiromichi Godo

Shuhei Nagatsuka

Satoru Ohshita

Takanori Matsuzaki

Yuki Okamoto

Yuichi Yanagisawa

Haruyuki Baba

Ryunosuke Honda

Shota Mizukami

Eri Sato

Yoshiyuki Kurokawa

Hideki Uochi

Koji Kusunoki

Yoshiaki Oikawa

Yasuhiro Jinbo

Satoru Okamoto

Takahiro Fukutome

Naoki Okuno

Tatsunori Inoue

Minato Ito

Tomonori Nakayama

Masahiro Takahashi

Yoko Tsukamoto

A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.

Semiconductor device, semiconductor wafer, and electronic device

A novel semiconductor device is provided. A component extending in a first direction, and a first conductor and a second conductor extending in a second direction are provided. The component includes a third conductor, a first insulator, a first semiconductor, and a second insulator. In a first intersection portion of the component and the first conductor, the first insulator, the first semiconductor, the second insulator, a second semiconductor, and a third insulator are provided concentrically. In a second intersection portion of the component and the second conductor, the first insulator, the first semiconductor, the second insulator, a fourth conductor, and a fourth insulator are provided concentrically around the third conductor.

Semiconductor device and electronic device

A semiconductor device with low power consumption is provided. In a cascode circuit including a first transistor provided on a low power supply potential side and a second transistor provided on a high power supply potential side, a source or a drain of a third transistor and a capacitor are connected to a gate of the second transistor. A gate of the first transistor is electrically connected to a back gate of the second transistor. An OS transistor is used as the third transistor.

A semiconductor device with low power consumption that is capable of non-destructive reading is provided. The semiconductor device includes a first transistor, a second transistor, a third transistor, a first FTJ element, and a second FTJ element. A first terminal of the first transistor is electrically connected to an output terminal of the first FTJ element, an input terminal of the second FTJ element, and a gate of the second transistor. A first terminal of the second transistor is electrically connected to a second terminal of the third transistor. For data writing, polarization is caused in each of the first FTJ element and the second FTJ element in accordance with data. For data reading, a voltage that does not cause a change in polarization is applied between the input terminal of the first FTJ element and the output terminal of the second FTJ element, a potential is supplied to the gate of the second transistor, and a current or voltage corresponding to data is obtained from the first terminal of the second transistor.

A semiconductor device in which an electrification phenomenon that leads to characteristic fluctuations, element deterioration, or dielectric breakdown is inhibited is provided. A first transistor, a second transistor, a third transistor, and a fourth transistor are included over a substrate; the fourth transistor includes a first conductor, a second conductor, a third conductor, and an oxide semiconductor; the first conductor is electrically connected to the semiconductor substrate through the first transistor; the second conductor is electrically connected to the semiconductor substrate through the first transistor; the third conductor is electrically connected to the semiconductor substrate through the first transistor; and the fourth conductor is electrically connected to the semiconductor substrate through the first transistor.

Semiconductor material and semiconductor device

A semiconductor device in which an electrification phenomenon that leads to characteristic fluctuations, element deterioration, abnormality in shape, or dielectric breakdown is inhibited is provided. The semiconductor device includes a first region and a second region over the same plane. The first region includes a transistor. The second region includes a dummy transistor. The transistor includes a first wiring layer, a semiconductor layer including an oxide and provided above the first wiring layer, a second wiring layer provided above the semiconductor layer, and a third wiring layer provided above the second wiring layer. The dummy transistor has the same area as one or more selected from the first wiring layer, the second wiring layer, the semiconductor layer, and the third wiring layer.

Semiconductor device

Malfunctions of a circuit is prevented and the reliability of a semiconductor device using the circuit is improved. The semiconductor device includes a first transistor, a second transistor, a load, and a wiring having a function of supplying a power supply potential to the load. A semiconductor layer of the first transistor includes an oxide semiconductor. A semiconductor layer of the second transistor includes an oxide semiconductor. A source and a drain of the first transistor are electrically connected to the wiring. A first gate of the first transistor is supplied with a reference potential. A source and a drain of the second transistor are supplied with the reference potential. A first gate of the second transistor is electrically connected to the wiring. The semiconductor layer of the first transistor includes a region overlapping with the wiring. The semiconductor layer of the second transistor includes a region overlapping with the wiring.

Semiconductor device comprising transistor, load, and wiring configured to supply power supply potential to the load

A display device with a novel structure is provided. The display device includes a first substrate provided with a plurality of pixels including a display element, and a second substrate including a first conductive layer provided with a plurality of first openings. The first conductive layer has a function of an antenna capable of transmitting and receiving a radio signal. The pixel and the first opening include a region where the pixel and the first opening overlap with each other. The second substrate includes an element layer. The element layer includes a transistor. The transistor has a function of an amplifier capable of amplifying the radio signal. The transistor each includes a semiconductor layer including a metal oxide in a channel formation region. The metal oxide contains In, Ga, and Zn.

Display device

Provided is a semiconductor device capable of retaining data for a long time. The semiconductor device includes a cell provided with a capacitor, a first transistor, and a second transistor; the capacitor includes a first electrode, a second electrode, and a ferroelectric layer; the ferroelectric layer is provided between the first electrode and the second electrode and polarization reversal occurs by application of a first saturated polarization voltage or a second saturated polarization voltage whose polarity is different from that of the first saturated polarization voltage; and the first electrode, one of a source and a drain of the first transistor, and a gate of the second transistor are electrically connected to one another. In a first period, the first saturated polarization voltage is applied to the ferroelectric layer. In a second period, a voltage having a value between the first saturated polarization voltage and the second saturated polarization voltage is applied to the ferroelectric layer as a data voltage.

Driving method of semiconductor device

To provide a mixer and a semiconductor device which each have a small circuit area and each of which operation capability is inhibited from being decreased due to heat. The mixer includes a differential portion, a current source, a first load, an input terminal, and a first output terminal; the differential portion includes a first and a second transistor; and each of the first and the second transistors includes a metal oxide in a channel formation region. A first terminal of each of the first and the second transistors is electrically connected to the input terminal and a current source and a second terminal of the first transistor is electrically connected to a first terminal of the first load and the first output terminal. The first load has a function of supplying a current between the first terminal and a second terminal of the first load by application of voltage to the second terminal of the first load, and the current source has a function of supplying a constant current to the current source from the first terminal of each of the first and the second transistors. The current source includes a transistor including silicon in a channel formation region, and the differential portion is positioned above the current source.

Mixer and semiconductor device

A low-power memory device in which a NAND flash memory and a controller are connected to each other with a short wiring, the controller and a cache memory are connected to each other with a short wiring, and signal transmission delay is small is provided. For example, the NAND flash memory is formed using a Si transistor formed with a single crystal silicon substrate. Since an OS transistor can be formed by a method such as a thin-film method, the cache memory formed using the OS memory can be stacked over the NAND flash memory. When the NAND flash memory and the cache memory are formed in one chip, the NAND flash memory and the controller can be connected to each other with a short wiring, and the controller and the cache memory can be connected to each other with a short wiring.

Memory device, operation method of memory device, data processing device, data processing system, and electronic device

A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.

Memory device having error detection function, semiconductor device, and electronic device

A novel semiconductor device is provided. A structure body extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction are provided. In a first intersection portion where the structure body and the first conductor intersect with each other, a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator are provided concentrically around a third conductor. In a second intersection portion where the structure body and the second conductor intersect with each other, the first insulator, the first semiconductor, the second insulator, a fourth conductor, the second semiconductor, and the third insulator are provided concentrically around the third conductor.

A semiconductor device is provided in which power consumption is reduced and an increase in circuit area is inhibited. The semiconductor device includes a high frequency amplifier circuit, an envelope detection circuit, and a power supply circuit. The power supply circuit has a function of supplying a power supply potential to the high frequency amplifier circuit, an output of the high frequency amplifier circuit is connected to the envelope detection circuit, and an output of the envelope detection circuit is connected to the power supply circuit. The power supply circuit can reduce the power consumption by changing the power supply potential in accordance with the output of the high frequency amplifier circuit. The use of an OS transistor in the envelope detection circuit can inhibit an increase in circuit area.

Semiconductor device including high frequency amplifier circuit, electronic component, and electronic device

A semiconductor device with high storage capacity is provided. The semiconductor device includes first to sixth insulators, first to third conductors, and first to third material layers. The first conductor overlaps with a first insulator and a first material layer. A first region of the first material layer overlaps with a second material layer, a second conductor, a second insulator, and a third insulator. The third material layer is positioned in a region including a second region of the first material layer and top surfaces of the second material layer, the second conductor, the second insulator, and the third insulator; a fourth insulator is positioned over the third material layer; the sixth insulator is positioned over the fourth insulator; and a fifth insulator is positioned over the sixth insulator. The third conductor is positioned over the fifth insulator overlapping with the second region of the first material layer. The first to third material layers include oxide containing indium, an element M (M is aluminum, gallium, tin, or titanium), and zinc.

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Kanagawa, Japan

Hitoshi Kunitake