Hitachi, Ltd.

Renesas Technology Corp.

Other

Hitachi Device Engineering Co., Ltd.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Engineering Co., Ltd.

Hitachi Ulsi Engineering Corp.

Solid State Storage Solutions LLC

Hitachi Microcomputer Engineering, Ltd.

Hitachi Vsli Engineering Corp.

Hitoshi Kume

Masataka Kato

Tetsuo Adachi

Katsutaka Kimura

Kazuhiro Komori

Toshihiro Tanaka

Satoshi Meguro

Toshiaki Nishimoto

Toshio Sasaki

Tadashi Muto

Takeshi Wada

Koichi Seki

Kazuyoshi Shoji

Yasurou Kubota

Yoshiaki Kamigaki

Takashi Kobayashi

Satoru Hanzawa

Hideaki Yamamoto

Hideaki Kurata

Takaaki Hagiwara

Naoki Kobayashi

Shoji Shukuri

Toshihisa Tsukada

Shunichi Saeki

Motoyasu Terao

Nozomu Matsuzaki

Tomonori Sekiguchi

Tokuo Kure

Makoto Saen

Toshiyuki Mine

Yoshitaka Sasago

Norikatsu Takaura

Tetsuya Ishimaru

Yasushi Goto

Masaharu Kinoshita

Minoru Ogushi

Syunichi Saeki

Toshiko Koizumi

Yoshinobu Nakagome

Norio Suzuki

Takashi Hashimoto

Kenji Takahashi

Yasuhiro Taniguchi

Akihiro Shimizu

Kazuyoshi Shiba

Keiichi Yoshida

Hiroaki Kotani

Toru Kaga

Atsushi Nozoe

Hiroshi Kawakami

Jiro Yugami

Masatada Horiuchi

Tsutomu Okazaki

Kazunori Furusawa

Shooji Kubono

Tetsufumi Kawamura

Yuzuru Ohji

Kikuo Kusukawa

Tsuyoshi Arigane

Masahiro Ushiyama

Kiyofumi Uchibori

Kouichi Seki

Yasuo Igura

Toshihisa Tsukuda

Keisuke Ogura

Hideo Tobe

Senichi Nishibe

Akemi Miura

Hidenori Takada

A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.

Method of manufacturing non-volatile memory module

A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.

Semiconductor device

To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

Nonvolatile semiconductor memory

Semiconductor device having user field and vendor field

A highly-reliable semiconductor device is realized. For example, each memory cell of a nonvolatile memory included in the semiconductor device is configured to include a source and a drain formed in a P-well, a memory node which is formed on the P-well between the source and the drain via a tunnel insulator and is insulated from its periphery, and a control gate formed on the memory node via an interlayer insulator. When a programming operation using channel hot electrons is to be performed in such a configuration, the P-well is put into an electrically floating state.

A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Method of manufacturing a semiconductor integrated circuit device having single-element type non-volatile memory elements

A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality of operations from a processing unit of the apparatus including an erase operation, the erase operation in the nonvolatile memory performs a threshold voltage moving operation and a verify operation, and the nonvolatile memory is capable of releasing the I/O bus during the erase operation to thereby allow accessing of other memories and/or system components. For example, during this erase operation, the Flash EEPROM is able to free the I/O data terminal such that the EEPROM becomes electrically isolated from the CPU. The CPU is then able to perform data processing by the system bus where information can then be transferred/received such as between other memories, e.g., ROM and RAM, and otherwise with the I/O port.

Nonvolatile memory apparatus having a processor and plural memories one or more of which is a nonvolatile memory having circuitry which performs an erase operation and an erase verify operation when the processor specifies the erase operation mode to the nonvolatile memory

Growing community of inventors

Musashino, Japan

Hitoshi Kume