Toshiba Memory Corporation

Hitoshi Kondo

Robert Reed

Narasimhulu Dharani Kotte

Senthil Thamgaraj

A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to a memory controller. A first portion of the plurality of multibit NAND media devices is configured to operate as a pSLC cache and a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area. In one embodiment, the pSLC cache comprises a first area for a pSLC write cache and a second area for a pSLC read cache.

Multibit NAND media using pseudo-SLC caching technique

A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to a memory controller. The SSD further includes one or more volatile memory devices communicatively coupled to the memory controller, where at least one of the one or more volatile memory devices has a read cache area. A first portion of the plurality of multibit NAND media devices is configured to operate as a pSLC write cache and a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area.

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San Jose, CA, United States of America

Hitoshi Kondo