Oki Electric Industry Co., Ltd.

Hitoshi Kokubun

Noboru Egawa

Shooji Kitazawa

Nobuhiro Kai

Keiichiro Takeda

Yuichi Ashizawa

A method of manufacturing a mask ROM for storing quaternary data enables short turn around time, makes refining cell sizes simple, and enables stable reading of data. Gaps are formed between word lines in the memory cell transistors and two diffusion areas in accordance with quaternary write data. A current runs between these diffusion areas only when one of these two areas which is adjacent a gap is used as a drain. Accordingly, quaternary data can be read by a first reading when the first diffusion area is a source and the other diffusion area is a drain, and by reading a second reading when the first diffusion area is used as a drain and the other diffusion area as a source.

Method of manufacturing non-volatile read only memory

A method of manufacturing a mask ROM for storing quaternary data enables short turn around time, makes refining cell sizes simple, and enables stable reading of data. Gaps are formed between word lines in the memory cell transistors and two diffusion areas. Impurities are doped into these gaps in accordance with quaternary write data when data is written. A current runs between these diffusion areas only when one of these two areas into which impurities have been doped is used as a drain. Accordingly, quaternary data can be read by a first reading when the first diffusion area is a source and the other diffusion area is a drain, and by reading a second reading when the first diffusion area is used as a drain and the other diffusion area as a source.

The mask ROM for storing quaternary data that enables a short turn around time, makes refining cell sizes simple, and that enables stable reading of data. Gaps are formed between word lines in the memory cell transistors and two n&plus; diffusion areas. n&plus; impurities are doped into these gaps in accordance with quaternary write data when data is written. A current runs between these diffusion areas only when one of these two areas into which impurities have been doped is used as a drain. Accordingly, quaternary data can be read by reading once when one diffusion area is a source and the other diffusion area is a drain and by reading again when the first diffusion area is used as a drain and the other as a source.

Non-volatile read only memory and its manufacturing method

A non-volatile semiconductor memory decreases a parasitic current as much as possible without using an electric separation means. This nonvolatile semiconductor storage apparatus has multiple memory cells rows having multiple memory cell transistors M,M,. . . whose gates are connected to word lines WL,, WL,. . . , respectively, and whose sources and drains are serially connected. This non-volatile semiconductor storage apparatus also has multiple column lines SBL,SVL,SVL,SBL,. . . which connect the connection nodes between the sources and drains of the memory cell transistors M,M,. . . in the column direction, a power source line PV,which supplies a prescribed electric potential to these column lines, first and second sense amplifiers which detect the electric potential level of the column lines or a current that flows through the column lines, sense column line selection means SS,SS,SS,SS,and,which connect column lines SBL,and SBL,connected to one terminal of selected memory cell M,and one terminal of selected memory cell M,respectively, to the first and second sense amplifiers A,and A,respectively. In this case, the memory cell M,is separated from the memory cell M,by a prescribed number of memory cells on the same memory cell row. This nonvolatile semiconductor storage apparatus further has power source supply column line selection means DS,DS,DS,DS,. . . which connect the column lines connected to the other terminals of the two selected memory cells to the power source line.

Non-volatile semiconductor memory capable of reducing parasitic current

Decoding circuit for a storing circuit

A voltage measuring circuit for detecting an unknown voltage in a semiconductor integrated circuit or the like. A voltage to be measured is converted into a first current by a current converting transistor, and a difference between the first current and a reference current is converted into a voltage. As a result, the voltage measuring circuit can be arranged without using a floating node, whereby it is possible to prevent variations in a desired voltage value to be measured.

Voltage measuring circuit

A semiconductor memory which is capable of measuring a threshold voltage in a memory cell. The semiconductor memory comprises memory arrays having a plurality of memory cells arranged in a matrix, means for selecting the memory cell, and a sense amplifier for comparing a current flowing through the selected memory cell with a current flowing through a dummy cell and provides an output indicative of a resultant comparison value. The memory cells each include a first switching means having a first transconductance at the time '1' is written in the memory cell and having a second transconductance at the time '0' is written in the memory cell, the value of the second transconductance being greater than the value of the first transconductance. The dummy memory cell includes a second switching means having a third transconductance value of which is in the middle between values of the first and the second transconductance. The memory cells and the dummy cell each have a gate coupled to respective external terminals. A selected one of the terminals receives increasing voltage.

Semiconductor memory with externally controlled dummy comparator

The data coincidence detecting circuit detects the coincidence of first data having bits with second data having bits. The data conincidence detecting circuit includes input lines, with the bits of the first data being supplied to respectively, a first storing circuit having first storing elements to store the bits of the first data therein and a second storing circuit having second storing elements to store the bits of the second data therein. The first element has first and second terminals and an input terminal connected to the input line through a node. The second element has first and second terminals and is connected to the first element. The first and second elements have a function for electrically connecting between the first and second terminals when the stored bit is a first state and disconnecting between the first and second terminals when the stored bit is a second state. The data coincidence detecting circuit further comprises a first power supplying circuit connected to the first storing circuit to selectively supply a first electric potential and a second electric potential, a second power supplying circuit connected to the second data storing circuit to selectively supply the first potential and the second potential, a detecting circuit to detect the electric potential of the nodes and to output a detecting signal on an output terminal thereof and an output circuit connected to the output terminal of the detecting circuit to decide the coincidence of the first data and the second data by the detecting signal.

Data coincidence detecting circuit

In a voltage detection circuit, a comparison voltage generator includes reference-setting capacitors, each having a first terminal connected to a comparison voltage node, and switching circuits provided in association with the respective reference-setting capacitors, each switching circuit selectively connecting a second terminal of the associated reference setting capacitor either to a first potential node or to a second potential node.

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Tokyo, Japan

Hitoshi Kokubun