Seiko Epson Corporation

Saiko Epson Corporation

Hitoshi Kobayashi

Satoru Kodaira

Kimihiro Maemura

Masataka Nomura

Yoshiki Makiuchi

Masaya Uehara

Takeshi Kumagai

Tadatoshi Nakajima

Takeshi Yasui

A semiconductor circuit includes an oscillation circuit; an output circuit that receives a first oscillation signal from the oscillation circuit and outputs a second oscillation signal; a DC circuit that receives a voltage based on a power supply voltage and outputs at least one of a DC voltage and a DC current; and a semiconductor substrate on which the oscillation circuit, the output circuit, and the DC circuit are formed. In a plan view of the semiconductor substrate, the DC circuit is disposed between the oscillation circuit and the output circuit.

Semiconductor circuit, oscillator, electronic apparatus, and moving object

A semiconductor circuit device includes: a semiconductor circuit provided on a main surface of a semiconductor substrate; and a thin film circuit element including a conductive thin film and disposed on the main surface of the semiconductor substrate. The semiconductor circuit is provided between the thin film circuit element and a peripheral portion of the semiconductor substrate in a plan view.

Semiconductor circuit device, electronic apparatus, and moving object

A nonvolatile memory device includes: a semiconductor layer of a first conductivity type in which a first region, a second region, and a third region are partitioned by an isolation insulating layer; a semiconductor section of a second conductivity type provided in the first region and functioning as a control gate; a semiconductor section of the first conductivity type provided in the second region; a semiconductor section of the second conductivity type provided in the third region; an insulating layer provided on the semiconductor layer in the first to third regions; a floating gate electrode provided on the insulating layer across the first to third regions; impurity regions of the first conductivity type provided on each side of the floating gate electrode in the first region; impurity regions of the second conductivity type provided on each side of the floating gate electrode in the second region and functioning as either a source region or a drain region; and impurity regions of the first conductivity type provided on each side of the floating gate electrode in the third region and functioning as either a source region or a drain region.

Nonvolatile memory device

A nonvolatile memory device, including a plurality of memory cell blocks, N memory cell blocks (N is an integer equal to or greater than 2) being arranged in a row direction, L memory cell blocks (L is an integer equal to or greater than 2) being arranged in a column direction, and each of the memory cell blocks including M memory cells (M is an integer equal to or greater than 2), a plurality of wordlines, a plurality of first control gate lines, a plurality of first control gate switches, a plurality of second control gate lines, and a plurality of bitlines.

Nonvolatile memory device and data write method for nonvolatile memory device

A semiconductor device includes: a semiconductor layer having a shading target region; a semiconductor element provided on the semiconductor layer in the shading target region; a first interlayer dielectric provided on the semiconductor element; a plurality of first shading layers provided on the first interlayer dielectric; a second interlayer dielectric provided on at least the first shading layers; and a second shading layer provided on the second interlayer dielectric and having a predetermined pattern. The second shading layer has such a pattern that the second shading layer is positioned at least between the adjacent first shading layers.

Semiconductor device

A semiconductor memory having a plurality of memory cells includes a first terminal that becomes a power supply terminal for the semiconductor memory, a second terminal that becomes a ground terminal for the semiconductor memory, a third terminal for inputting a burn-in mode signal to place the semiconductor memory in a burn-in mode and a fourth terminal for inputting an external clock signal. The semiconductor memory further includes an address signal generation section that generates an address signal for selecting each of the plurality of memory cells based on counting of the clock signal while the burn-in mode signal is input. A data signal generation section generates a data signal based on the clock signal while the burn-in mode signal is input. A data writing section writes data of the data signal in the memory cells selected by the address signal.

Growing community of inventors

Suwa, Japan

Hitoshi Kobayashi