Shin-etsu Handotai Co., Ltd.

Nanoteco Corporation

Hitoshi Ikeda

Akio Nakamura

Kingo Suzuki

Masato Yamada

Toru Takahashi

Yuichi Matsumoto

Tetsuro Aoyama

Nobuhiko Noto

Takao Takenaka

Shinji Nozaki

Hiroshi Morisaki

Kazuo Uchida

Masahisa Endo

Toshio Otaki

Yukari Suzuki

Masayoshi Obara

Yasutsugu Kaneko

A method for manufacturing a SiC single crystal reducing crystallinity degradation at a wafer central portion wherein a growth container surrounds a heat-insulating material with a top temperature measurement hole, a seed crystal substrate at an upper portion inside the container, and a silicon carbide raw material at a lower portion of the container and sublimated to grow a SiC single crystal on the seed crystal substrate. A center position hole deviates from a center position of the seed crystal substrate and moves to the periphery side of the center of the seed crystal substrate. A SiC single crystal substrate surface is tilted by a {0001} plane and used as the seed crystal substrate. The SiC single crystal grows with the seed crystal substrate directed to a normal vector of the seed crystal substrate basal plane parallel to the main surface and identical to the hole in a cross-sectional view.

Method for manufacturing a silicon carbide single crystal by adjusting the position of a hole in a top of the growth container relative to the off angle of the silicon carbide substrate

A method for manufacturing a SiC single crystal having a growth container surrounded by a heat-insulating material, a seed crystal substrate disposed inside a top at a center of the container, a silicon carbide raw material disposed at a bottom of the container to sublimate and grow a SiC crystal to allow a center of the hole to deviate from a center position of the seed substrate to a position on a periphery side, a SiC substrate having a main surface tilted from a {0001} plane wherein a basal plane is used and grown with the seed substrate so that a direction of a component of a normal vector of the basal plane of the seed substrate parallel to the main surface and an eccentric direction of the hole are opposite directions in a cross-sectional view including the center of the seed substrate and the center of the hole.

Each second electrode formed on a second main surface of a compound semiconductor layer of a light emitting device has an alloyed contact layer disposed contacting the second main surface, aimed at reducing contact resistance with the compound semiconductor layer, and a solder layer connecting the alloyed contact layer to the conductive support. The solder layer forms therein a Sn-base solder layer disposed on the alloyed contact layer side having a melting point lower than the alloyed contact layer, and a Au&#x2014;Sn-base solder layer disposed contacting the Sn-base solder layer opposed to the alloyed contact layer side, containing total Au and Sn of 80% or more, and having a melting point higher than the Sn-base solder layer. This configuration can provide excellent reliability of bonding between the Au&#x2014;Sn-base solder layer and the alloyed contact layer, and consequently less causative of delamination of the Au&#x2014;Sn-base solder layer.

Light emitting device and method of fabricating light emitting device

Aiming at providing a method of fabricating a light emitting device having an AlGaInP light emitting section, less causative of crack by cleavage, on the edge portions on the back surface of the device chip in process of dicing or breaking, a light emitting device wafer is diced along a dicing line inclined at an angle of 15&#xb0; to 30&#xb0;, both ends inclusive, away from a dicing line angle reference direction defined as the &#x3c;110&#x3e; direction on the (100) main surface.

Method of fabricating light emitting device and thus-fabricated light emitting device

A light emitting device wafer is fabricated, having a light emitting layer section, composed of AlGaInP, based on a double heterostructure and a GaP light extraction layer disposed on the light emitting layer portion, having a first main surface thereof appearing on the first main surface of the wafer, so as that a P-rich off-angled {100} surface, having a higher existence rate of P atoms than an exact {100} surface, appears on the first main surface the GaP light extraction layer. The main first surface of the GaP light extraction layer is etched with an etching solution FEA so as to form surface roughening projections. Therefore, it provides a method of fabricating a light emitting device capable of applying surface roughening easily to the GaP light extraction surface having the {100} surface, off-angled to be P-rich, as a main surface thereof.

Method of fabricating light emitting device

A light emitting device chip is obtained by dicing a light emitting device wafer having a light emitting layer sectionbased on a double heterostructure in which a first-conductivity-type cladding layer, an active layerand an second-conductivity-type cladding layer, each of which being composed of a compound semiconductor having a composition allowing lattice matching with GaAs, out of compound semiconductors expressed by formula (AlGa)InP (where, 0&#x2266;x&#x2266;1, 0&#x2266;y&#x2266;1), are stacked in this order, and having the () surface appeared on the main surface thereof, and GaP transparent semiconductor layersstacked on the light emitting layer sectionas being agreed with the crystal orientation thereof, so that the {100} surfaces appear on the side faces of the GaP transparent semiconductor layer. Accordingly, there can be provided a method of fabricating a light emitting device having the AlGaInP light emitting layer section and the GaP transparent semiconductor layers, less causative of failures such as edge chipping during the dicing.

A light emitting device wafer having a light emitting layer sectionhaving an AlGaInP-base double heterostructure, and a GaP light extraction layerdisposed on the light emitting layer section so as to allow a first main surface thereof to compose a first main surface of the wafer is fabricated so that the first main surface of the GaP light extraction layer appears as the () surface. The first main surface of the GaP light extraction layercomposed of the () surface is etched using an etching solution for surface roughening to thereby form surface roughening projections. Accordingly, there can be provided a method of fabricating a light emitting device having the GaP light extraction layer agreed with the () main surface, capable of readily subjecting the () main surface to surface roughening.

A light emitting devicehas a structure in which a p type InGaAs layeras an electrode contact layer and an ITO electrode layeras an oxide transparent electrode layer are formed in the order in a first major surfaceside of a light emitting layer section. In a second major surfaceside of the light emitting layer section, an n type InGaAs layeras an electrode contact layer and an ITO electrode layeras an oxide transparent electrode layer are formed in the order. The ITO electrode layersandtogether with the p type InGaAs layerand the n type InGaAs layerare formed on the respective both major surfacesandof the light emitting layer sectionso as to cover the respective both major surfacesandin the entirety thereof.

Light emitting device

The main surface on the side of a p-type layer of a GaP-base semiconductor is defined as a first main surface, and the main surface opposite thereto as a second main surface. The second main surface is lapped and then etched using aqua regia to thereby collectively form thereon specular concave curved surfaces which swell inwardly into the semiconductor substrate in order to enhance total reflection of light. On the other hand, the area on the surface of semiconductor substrate excluding that for forming a first contact layer and excluding the second main surface are subjected to anisotropic etching to thereby collectively form outwardly-swelling convex curved surfaces in order to reduce total reflection of light. A second contact layer (second electrode) to be formed on the second main surface is composed of an alloy of Au, Si and Ni, and a first contact layer to be formed on the first main surface is composed of an alloy of Au as combined with either of Be and Zn. This successfully provides a GaP-base semiconductor light emitting device which can ensure a satisfactory level of improvement in the luminance even though the emission mechanism thereof relies upon indirect transition.

GaP-base semiconductor light emitting device

An semiconductor substrate processing apparatus of the type including a furnace tube associated with a fluid supply unit and a fluid discharge unit, wherein the furnace tube is rotatably supported by pairs of confronting rollers and rotated by a motor under the control of a controller in order to achieve various kinds of processing of semiconductor substrates within the furnace tube. With this rotatable furnace tube, the apparatus exhibits high radial temperature uniformity and is able to prevent deformation of the furnace tube.

Growing community of inventors

Annaka, Japan

Hitoshi Ikeda