Sanyo Electric Co., Ltd.

Hitoshi Ando

Minoru Hamada

The operational method is disclosed, for storing analog data in an electrically programmable and erasable memory cell. The memory cell includes a transistor having a source, a drain, a control gate and a floating gate, where the source, the drain and a channel region therebetween being defined in a semiconductor substrate, the floating gate operating to accumulate charge and being capacitively coupled to the source and the control gate. The method includes the steps of: erasing data in the memory cell, and storing analog data in the memory cell. The erasing step including at least the steps of: i) applying a predetermined first erase voltage to the control gate, ii) applying a ground voltage to the drain to erase the memory cell, wherein charges moved from the channel region are accumulated in the floating gate, thereby erasing data in the memory cell. The storing step including at least the steps of: i) applying a predetermined write voltage to the control gate, ii) applying a voltage corresponding to the analog data to be stored to the drain to write the analog data in the memory cell, whereby charges are moved to the control gate from the floating gate being associated with the analog data to be stored.

Growing community of inventors

Gifu-ken, Japan

Hitoshi Ando