Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Video and Information System, Inc.

Hitachi Computer Electronics Co., Ltd.

Hitoshi Abe

Masamori Kashiyama

Katsumi Ogiue

Kinya Mitsumoto

Satoru Isomura

Hiroshi Murayama

Kazuhiro Akimoto

Masami Usami

Yasuhiko Hatakeyama

Yoshikuni Kobayashi

Tsutomu Takagi

Katsutoshi Tajima

Shigeo Nagashima

Yoshio Kiriu

Toshimitsu Ando

Shigeko Yazawa

Naozane Yoshida

Nobuhiro Washiya

Kanji Masuyama

Kiyotaka Doi

Tamotsu Hirota

An apparatus for adding isopleths to image data includes an input device for sequentially inputting image data to be displayed on an image screen of a display device, a horizontal delay circuit for delaying the inputted data by one horizontal scanning period, a column comparator for comparing the inputted data, that is, a sample, with a delayed sample from the horizontal delay circuit to thereby generate a signal indicating a sample to be converted into isopleth data, a sample delay circuit for delaying the sample outputted from the horizontal delay circuit by one sampling period, a row comparator for comparing the sample outputted from the horizontal delay circuit with the sample outputted from the sample delay circuit to thereby generate a signal indicating a sample to be converted into isopleth data, and an isoplete data generator responsive to the output of the column and row comparators for replacing the indicated input sample by predetermined distinguishable data and for outputting the predetermined distinguishable data to the display device.

Isopleth generator for applying isopleths to digital picture data and

Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.

Semiconductor integrated circuit device with two variable delay lines in

Frames of digital data each representing a single picture of a video motion picture display are handled in a computer system with an extended memory operating in parallel with a computer system instruction processor and main memory to bypass the computer system input/output processor for continuously outputting the video information on a real time basis. The outputted data may be recorded continuously at a constant data rate for an entire motion picture worth of information or actually displayed on the video display on a real time basis. The extended storage has a memory larger than the main memory, where all of the frame data is stored and read out in high speed bursts to a buffer that continuously reads the data out of the buffer for outputting. At least a start command and a starting address in the extended memory are contained within the main memory to be read out and decoded by the instruction processor and computer system memory storage control, for transfer to the extended memory, where they are used to start the program, which includes extended memory control words stored in the main memory, which control words are decoded and executed in the extended memory in parallel with the computer system instruction processor. Addresses of succeeding frames are generated and decoded and used for fetching entirely within the extended memory, for memory areas according to indirect addressing. The extended memory has external data transfer and internal data transfer registers that hold command words for respective transferring programs that may be operated in parallel, with conflict between external transfer and internal transfer being decided in favor of external transfer to assure continuous data outputting.

Information processing system

A method of controlling an image memory system wherein non-interlace image data is written into the odd field and the even field memories, and the contents written into the odd field and even field memories are respectively read out so as to be converted into interlace image data. Each line of the non-interlace image data is alternately written into the odd field and even field memories in units of a plurality of dots. If the plurality of dots include dots for the odd field and dots for the even field, the image data of the plurality of dots are simultaneously written into both the odd field memory and the even field memory. When reading the image data out from the odd field memory, the image data for the even field written into the odd field memory is invalidated. Similarly, when reading the image data out from the even field memory, the image data for the odd field written into the even field memory is invalidated. With this structure, writing/reading operation to the image memory can be performed at high speed without error even when the total number of dots on one line are not divisible by the number of dots to be written into the memories in parallel. Further, it is not necessary to change the output specification of the output device which outputs the image data, such as a computer.

Method of controlling image memory system for non-interlace/interlace

Semiconductor device for a ram disposed on chip so as to minimize

In a vector processor in which a plurality of load/store pipelines from a plurality of arithmetic units and a main storage are used for input/output operations of vector data on a plurality of vector registers in a parallel fashion, vector data is communicated between the respective modules constituting a physically closed system. A sequence of odd-numbered vector data elements and a sequence of even-numbered vector data elements each having a phase difference of a half of a period of a basic machine cycle are communicated at a speed of the basic machine cycle. The module includes vector registers, each vector register is constituted with two RAM arrays being independently addressable and being capable of performing read and write operations at a speed which is twice the basic machine cycle. The two vector data element sequences are converted into a vector data element sequence having a speed which is twice the machine cycle such that the respective vector data elements are alternately written and read in the RAM arrays at a speed which is twice the basic machine cycle. The vector data element sequence thus read out is converted into a sequence of odd-numbered vector data elements and even numbered vector data elements each having a speed of the basic machine cycle and thus the attained vector data element sequences are output.

Vector processor

In a vector processing unit, a vector register undergoing the first readout operation is simultaneously subjected to the second reading operation. The data obtained by the first readout operation and the data obtained by the second readout operation are respectively sent to separate resources executing different instructions.

Vector processing unit capable of reading vector data from a vector

A data processor has a plurality of vector registers capable of reading and writing in parallel; a plurality of ALU's; a plurality of sending circuits, one for each of said vector registers, each for updating a read address for the corresponding vector register requested by a succeeding instruction within such a limit that said read address does not pass a write address for said corresponding vector register requested by a preceding instruction and sending out a read data together with a data valid signal for each updating; circuits for sending the data and the data valid signals from said plurality of sending circuits to the ALU's requested by the corresponding instructions; and circuits, one for each of said ALU's, each for controlling the corresponding ALU such that when the data valid signals have been received from all of the vector registers necessary to execute the instruction which uses the corresponding ALU, the corresponding ALU operates on the data supplied with said data valid signals and sends out a data valid signal.

Growing community of inventors

Hadano, Japan

Hitoshi Abe