Kabushiki Kaisha Toshiba

Nuflare Technology, Inc.

Hitomi Yamaguchi

Kazuyuki Higashi

Noriaki Matsunaga

Hiroshi Matsumoto

Atsuko Sakata

Hirokazu Ezawa

Hirofumi Morita

Tomio Katata

Yoshiaki Shimooka

Seiichi Omoto

Yoshikuni Goshima

Kei Obara

Miyoko Shimada

A semiconductor device according to an embodiment includes: a substrate including a plurality of through holes provided at predetermined intervals along a first direction in a substrate surface and along a second direction intersecting the first direction in the substrate surface; an insulating layer provided on the substrate, the insulating layer being penetrated by the through holes; a plurality of first electrodes provided on the insulating layer, the first electrodes being adjacent to the respective through holes in the first direction; a plurality of second electrodes provided on the insulating layer, the second electrodes being adjacent to the respective through holes in the first direction, the second electrodes being provided to face the first electrodes, the second electrodes being held at a predetermined potential; and a wiring layer provided on the insulating layer, the wiring layer electrically connecting the adjacent second electrodes.

Semiconductor device, multi-charged-particle beam writing apparatus, and multi-charged-particle beam exposure apparatus

A semiconductor device is the semiconductor device which includes more than one field effect transistor having a gate electrode to which an electrical interconnect wire is connected and a gate insulation film with a thickness of 6.0 nm or less and which comprises a first transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film, a second transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film with the thickness of gate insulation film being less than the thickness of the gate insulation film of the first transistor group, and a semiconductor substrate on which the first and second transistor groups are mounted together in a mixed manner, wherein an antenna ratio which is a ratio of the area of a wire to the gate area of a gate electrode is such that the maximum value of the second transistor group is greater than the maximum value of the first transistor group.

Wiring layout of semiconductor device and design method of the same

There is here disclosed a manufacturing method of a semiconductor device, comprising providing a first film by a PVD process in a recess formed in at least one insulating film, the first film containing at least one metal element belonging to any one of the groups-A,-A, and-A, continuously providing a second film by at least one of CVD and ALD processes on the first film without opening to atmosphere, the second film containing at least one metal element belonging to any one of the groups-A,-A, and-A, continuously providing a third film by the PVD process on the second film without opening to the atmosphere, the third film containing at least one metal element belonging to any one of the groups-A,-A, and-A, continuously providing a first Cu film on the third film without opening to the atmosphere, and heating the Cu film.

Manufacturing method of semiconductor device

Growing community of inventors

Yokohama, Japan

Hitomi Yamaguchi