Kabushiki Kaisha Toshiba

Hitomi Kawaguchiya

Tohru Ozaki

Masami Aoki

Takeshi Hamamoto

Akira Nishiyama

Takashi Yamada

Satoshi Inaba

Atsushi Murakoshi

Yoshiaki Matsushita

Kazuya Matsuzawa

Osamu Arisumi

Yutaka Ishibashi

Naoyuki Shigyo

Makoto Yoshimi

Mamoru Terauchi

Mitsuo Koike

In one embodiment, a sample processing method includes placing a sample on a sample placing module, and setting first processing boxes on one side of slice formation scheduled regions of the sample, and second processing boxes on the other side thereof. The method includes processing the sample by performing a primary scan which sequentially scans the first processing boxes with a continuously generated ion beam, and a secondary scan which sequentially scans the second processing boxes with a continuously generated ion beam, to form slices of the sample. The primary and secondary scans are performed so that a first scanning condition for scanning first regions within the first and second processing boxes is set different from a second scanning condition for scanning second regions between the first processing boxes and between the second processing boxes, to allow frame portions of the sample to remain in the second regions.

Sample processing method

A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

Insulated-gate transistor having narrow-bandgap-source

A semiconductor memory device comprises a semiconductor substrate, a plurality of memory cells including a plurality of MOS transistors, each having a source, a drain and a gate, and a plurality of capacitors formed on the semiconductor substrate in a matrix manner, an interlayer insulating film formed on the memory cells and having a plurality of openings selectively formed, a plurality of plug electrodes formed in the openings of the interlayer insulating film, a plurality of bit lines, each bit line being connected to one of the source and the drain of each of the MOS transistors through a corresponding one of the plug electrodes, and a plurality word lines, each word line being the gate of each of the MOS transistors. The capacitors each comprise a storage node electrode having a cylindrical portion layered on another one of the source and the drain of each of the MOS transistors, a capacitor dielectric film formed on the storage node electrode, and a plate electrode formed to be opposed to at least the storage node electrode interposing the capacitor dielectric film therebetween. The bit lines are formed on the interlayer insulating film and connected to the upper surface of the plug electrode. The plug electrode has a pad electrode comprised of a lower side conductive member formed with a same layer as the storage node electrode and a cylindrical side wall conductive member, and an upper side conductive member formed on the pad electrode.

Semiconductor memory device having cylindrical capacitors

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Yokohama, Japan

Hitomi Kawaguchiya