Qualcomm Incorporated

Hithesh Hassan Lepaksha

Darshan Kumar Nandanwar

Sharath Kumar Nagilla

Venkata Biswanath Devarasetty

Nirav Narendra Desai

Sagar Bamashetti

Kartik Gunvantbhai Desai

Linga Achuta Ram Kumar Nimmala

Apparatus and methods for maintaining approximate uniformity of aging of equivalent processing circuits in a pipeline stage(s) in a processor are disclosed. The processor includes one or more processing units that include one or more pipelines. A pipeline includes a series of pipeline stages each of which performs a particular function. In this regard, the processor also includes an age management circuit (AMC) configured to store performance factors indicative to aging of the equivalent processing circuits in a pipeline stage. In response to work input into a given pipeline stage, the AMC is further configured to route the work input to one of the equivalent processing circuits in the pipeline stage based on the stored performance factors. In so doing, the AMC controls the frequency of use of the equivalent processing circuits in its pipeline stage to substantially maintain uniform aging of the equivalent processing circuits.

Maintaining approximate uniformity of aging of equivalent processing circuits in a pipeline stage(s) in a processor

A method includes executing a first pointer authentication instruction, including a first pointer authentication code, on a pointer in a speculative path of a pipeline. The method also includes determining whether the first pointer authentication code for the pointer fails. The method further includes determining whether the first pointer authentication code for the pointer differs from a previous pointer authentication code for the pointer in response to the first pointer authentication code failing. The method still further includes incrementing a failure counter in response to determining that the first pointer authentication code for the pointer failed and that the first pointer authentication code for the pointer differs from the previous pointer authentication code for the pointer. The method additionally includes determining whether the failure counter is greater than a threshold value and performing a defensive action in response to the failure counter being greater than the threshold value.

Systems and methods for defending against side channel attacks to speculative execution of processor pipeline instructions

A processing unit including a dynamically allocatable vector register file for non-vector instruction processing is disclosed. The processing unit includes an integer execution circuit and integer register file for processing integer instructions. The processing unit also includes a vector execution circuit and a vector register file for processing vector instructions. The integer and vector register files are each sized at design time. A processing unit may be called upon to execute varying workloads that vary between integer and vector operations. Rather than statically dedicating the entire vector register file to vector registers, the processor is configured to dynamically allocate a portion(s) of the vector registers in the vector register file for use in the execution of integer instructions.

Processing unit including a dynamically allocatable vector register file for non-vector instruction processing

Systems and methods for reducing data movement when performing large-sized memory transactions in a memory hierarchy are provided. For certain preselected types of large-size memory transactions, such as memset and memcopy operations, for example, logic of the processor determines whether the type of memory transaction being queued is one of the preselected types for which alteration of the path of data movement is an option. Logic of the processor also determines whether the size of the memory block associated with the transaction is sufficiently large to warrant altering the path of data movement. If the type is one of the preselected types and the size of the memory block is sufficiently large, logic of the LLC controller selects an altered path for data movement that reduces data movement and performs the transaction using the altered path.

Methods and systems for altering the path of data movement for large-sized memory transactions

A method of execution unit (EU) sharing between processor cores is described. The method includes encountering a structural hazard associated with an issued instruction in an instruction queue of a dispatch stage inside an active processor core. The method also includes issuing a request for an idle execution unit of an inactive processor core. The method further includes sending a transaction containing source operands of the issued instruction, and a word address of a result buffer as a destination operand to an allocated EU of the inactive processor core. The method also includes replacing the issued instruction in the instruction queue with a load operation to forward a result of the issued instruction from the result buffer based on the word address.

Execution unit sharing between processing cores in a cluster of a system-on-chip (SoC)

Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting a number of cache lines that satisfy an eviction criteria based on a deterministic cache eviction policy in each cache way of a group of cache ways; selecting at least one cache way from the group for collapse, based on its corresponding number of cache lines that satisfy the eviction criteria; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.

Performance aware partial cache collapse

Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting, in each cache way of a group of cache ways, a number of dirty cache lines having dirty bits indicating the cache line has been modified; selecting, from the group, at least one cache way for collapse, based on its corresponding number of dirty cache lines; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.

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Hyderabad Telangana, India

Hithesh Hassan Lepaksha