Cadence Design Systems, Inc.

Hitesh Marwah

Arnold Ginetti

Pawan Fangaria

Sanjib Ghosh

Vandana Gupta

Mahendra Singh Khalsa

Arnold Jean Marie Gustave Ginetti

Chayan Majumder

Amit Kumar

Sandipan Ghosh

Sunil Prasad Todi

Arbind Kumar

Disclosed is an improved approach to implement electronic designs by performing altitude-based re-layering for I/Os. The altitude-based die stack layers allows N number of die stack layers corresponding to the actual altitudes of the I/Os in the design.

Method and system to implement altitude based I/O re-layering for electronic and photonic designs

The present disclosure relates to a computer-implemented method for electronic circuit design awareness. Embodiments may include providing, using a processor, an electronic design having a package layout and a die layout associated therewith. Embodiments may also include displaying at a graphical user interface, the package layout and allowing, at the graphical user interface, a user to edit the package layout. Embodiments may further include determining, using the processor, an impact of the edit on the die layout and in response to the edit, mirroring the edit at the die layout.

System, method and computer program product for design rule awareness associated with die and package electronic circuit co-design

A system and method for an interactive circuit layout design that provides spatially adaptive overlay indicative of parametric properties. A physical layout of an electrical circuit product is rendered on a display. At least one net of the physical layout is delineated into a plurality of net segments each having at least one physical property parametrically specified in a value therefor. For each net segment, a corresponding segment indicator is selectively rendered on the display, adaptively positioned and spatially mapped to the net segment corresponding thereto as a symbolic surrogate for the corresponding net segment within the physical layout. Selection of a net segment actuates determination of a behavior of the electrical circuit product during an operation consistent with an electrical response of the corresponding net segment. Editing of a net of the physical layout delineates a plurality of updated net segments for the edited net exclusive of other nets.

Electronic circuit design editor with overlay of layout and schematic design features

According to various embodiments of the invention, a system and method for editing process rules for circuit design through a graphical editor is provided. In some embodiments, the graphical editor is a circuit design tool that provides the user of the tool, such as a circuit designer or process engineer, the ability to visualize, modify, create, or remove process rules through a graphical user interface ('GUI'). These process rules, also known as constraints or circuit design constraints, relate to the layout of circuits and is grouped into constraint groups (also known as 'circuit design constraint groups') that can be associated to specific circuit design objects.

System and method for process rules editors

A circuit design process is presented that includes a block placement operation, followed by global routing based upon the initial placement of the blocks. Congestion data is generated from the global routing and, in an automated process, the blocks are placed again based upon the congestion data to reduce the routing congestion of the design. This can be used as part of a custom layout design process, for example.

Congestion aware block placement

A circuit design process for the reduction of routing congestion is described. This process includes a block placement operation, an initial pin optimization for the block placement, and global routing based upon the initial pin optimization. Congestion data is generated from the global routing and, in an automated process, the pins are re-optimized, based upon the congestion data. This process can be used as part of a custom layout design process, for example.

Congestion aware pin optimizer

Techniques are present for designing of integrated circuits. Both custom design data and synthesized digital design data are received and merged into a design database in an automated process. The design database is then made accessible to layout tools so that the layout tools may operate upon it. These layout tools can include, but are not limited to, custom tools, digitals, or a combinations of these.

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Noida, India

Hitesh Marwah