Qualcomm Incorporated

Apple Inc.

Hitesh Kumar Gupta

Eric W Mahurin

Colin Beaton Verrilli

Erich Plondke

Greg M Hess

Rexford Alan Hill

Naveen Javarappa

Ahmad Mahmoud Radaideh

An aspect of the disclosure relates to a data processing system, including: an input medium configured to include a first set of blocks of data including a first set of block of compressed data and a first set of metadata, respectively; an output medium configured to include a first set of blocks of decompressed data each having a predetermined number of decompressed elements; and a set of single instruction multiple data (SIMD) processors configured to: access the first set of blocks of data from the input medium, respectively; decompress the first set of blocks of compressed data to generate the first set of blocks of decompressed data based on the first set of metadata, respectively; and provide the first set of blocks of decompressed data to the output medium, respectively.

Single instruction multiple data (SIMD) sparse decompression with variable density

A device includes a scoreboard and a processor. The scoreboard includes scoreboard entries configured to store information regarding one or more uncompleted memory access operations. The scoreboard also includes a dependency matrix configured to store dependency information corresponding to the scoreboard entries. The processor is configured to retrieve a first memory access instruction that indicates a first address range of a first memory access operation, and to add an indication of the first memory access instruction to a first scoreboard entry. The processor is further configured to, based on determining that the first address range at least partially overlaps a second address range associated with a second scoreboard entry that corresponds to a second memory access instruction, set an element of the dependency matrix to have a has-dependency value indicating a dependency of the first scoreboard entry on the second scoreboard entry.

Memory access management

A zero keeper circuit includes a dynamic input PFET connected to a source, an output, and a dynamic input. The circuit also includes a clock input NFET connected to the output, a pull-down node, and a clock input. The circuit also includes a dynamic input NFET connected to the pull-down node, a reference voltage, and the dynamic input. The circuit also includes a feedback PFET and a clock input PFET connected in series between the source and the output. The feedback PFET receives a feedback signal and the clock input PFET receives the clock input. The circuit also includes a feedback NFET connected to the output and the node. The feedback NFET is configured to couple the output to the node based on the feedback signal. The circuit also includes a NOR gate configured to provide the feedback signal based on the output and a bypass input.

Zero keeper circuit with full design-for-test coverage

Growing community of inventors

Santa Clara, CA, United States of America

Hitesh Kumar Gupta