Intel Corporation

Arista Networks, Inc.

Hitesh Ahuja

Robert F Krick

Chan W Lee

Per H Hammarlund

Alan Beecher Kyker

Joseph F Rohlman

William Alexander

Bret L Toll

Michael J St Clair

John Allan Miller

Dipankar Bhatt Acharya

John Alan Miller

Min H Teng

Darrin Machay

A network switch device includes an L1 switch having a first set of external ports and a first set of internal ports. The network switch device further includes an L2+L3 switch having a second set of internal ports, the L2+L3 switch operatively coupled to the L1 switch via the first set of internal ports and the second set of internal ports.

Low-latency network switching device with latency identification and diagnostics

A system and method for calculating latency including a latency calculation device configured to: receive an enqueue notification relating to a packet enqueue operation and including a queue identifier, increment an enqueue counter, and determine that a latency calculation flag is not set. Based on the determination that the latency calculation flag is not set, the latency calculation device is configured to: determine a first time corresponding to the enqueue notification, store the first time, store a latency start count, and set the latency calculation flag. The latency calculation device is also configured to: receive a dequeue notification relating to the packet dequeue operation and including the queue identifier, increment a dequeue counter, determine that the latency start count and the dequeue counter values match, determine a second time corresponding to the dequeue notification, and calculate latency as the difference between the first time and the second time.

Method and system for non-tagged based latency calculation

An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

System and method for storing immediate data

A method and apparatus for decompressing relative addresses. A compressed relative address is retrieved from one or more micro-operation entries of a micro-operation storage and an uncompressed relative address is reconstructed from the compressed relative address and an instruction pointer (IP) address associated with the head of the micro-operation storage line in which the compressed relative address was stored. IP-relative addresses may be computed in a manner similar to relative branch targets, then compressed and stored in one or more micro-operation entries of a micro-operation storage line to be reconstructed later according to an IP address associated with the respective micro-operation storage line in which their compressed counterpart was stored.

Method and apparatus for decompressing relative addresses

A method and apparatus for compressing relative addresses and for storage of compressed relative addresses. A relative virtual address is computed in a particular stage of a processor pipeline and then compressed according to one or more compression techniques for storage in a micro-operation storage. A compressed relative address is retrieved from one or more micro-operation entries of the micro-operation storage and an uncompressed virtual address is reconstructed from the compressed relative address and an instruction pointer (IP) address associated with the head of the micro-operation storage line in which the compressed relative address was stored. IP-relative addresses may be computed in a manner similar to relative branch targets, then compressed and stored in one or more micro-operation entries of a micro-operation storage line to be reconstructed later according to an IP address associated with the respective micro-operation storage line in which their compressed counterpart was stored.

Method and apparatus for compressing relative addresses

A method and system for reducing a latency of microprocessor instructions in transit along an instruction pipeline of a microprocessor by bypassing, at certain times, a fill buffer located between an instruction source and a trace cache unit on the instruction pipeline. The signal path through the fill buffer to the trace cache unit represent a first signal path. In the instruction pipeline, a second signal path is also provided, one which also leads instructions to the trace cache unit, not through the fill buffer, but through a latch provided on the second instruction path. If the latch is enabled, a set of instructions appearing at the input of the fill buffer is transmitted through the latch along the second instruction path and to the trace cache. As a result, the fill buffer is bypassed and a reduced latency for the bypassed instructions is achieved along the instruction pipeline.

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Portland, OR, United States of America

Hitesh Ahuja