Stmicroelectronics International N.v.

Synopsys, Inc.

Hiten Advani

Mayank Kumar Singh

Daljeet Kumar

Phalguni Bala

Nishu Kohli

Sanjeev Chopra

Akshay Adlakha

Manohar Raju Ksv

ManoharRaju Ksv

A circuit to multiplex supply voltages may include a set of chains of transistors. Each chain of transistors may correspond to a voltage supply that is desired to be multiplexed and may include a set of transistors coupled in series. A first end terminal of each chain of transistors may be coupled to a corresponding voltage supply, and a second end terminal of each chain of transistors may be coupled to an output terminal of the circuit. A given supply voltage may be selected by turning on transistors in a chain of transistors that corresponds to the given supply voltage and turning off transistors in other chains of transistors.

Scalable supply multiplexer circuit

According to an embodiment, a circuit includes a protection voltage generator coupled to a first voltage node, a second voltage node, and a ground voltage node, the protection voltage generator configured to generate a plurality of protection voltages at a first plurality of nodes based on the first voltage node and the second voltage node, and a voltage protection ladder coupled between the first voltage node and a low voltage circuit, the voltage protection ladder coupled to the plurality of protection voltages at the first plurality of nodes, the voltage protection ladder configured to generate a first low voltage based on the first voltage node and the plurality of protection voltages.

Scalable protection voltage generation

Scalable protection voltage generator

An embodiment of a pre-emphasis circuit, an embodiment of a method for pre-emphasizing complementary single-ended signals, an embodiment of a transmitter, and an embodiment of a communication system.

Pre-emphasis circuit

An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.

Impedance calibration circuit and method

A system and method for utilizing multiple configurable lanes for clock and data transfer in source synchronous systems that may utilize a clock signal from another source for interpreting data received from the source. In an embodiment, a system may include a transmitter configured to transmit at least one clock signal and at least one data signal to a receiver device. The receiver device may have at least one clock lane and at least one data lane for receiving signals from the transmitter device. The clock lane(s) and data lane(s) can be arranged in any order as per requirement of system design. In the receiver, after manufacture, each data lane may be configured to be clocked by any clock lane.

Configurable lane architecture in source synchronous systems

A memory cell is formed by storage latch having a true node and a complement node. The cell includes a write port operable in response to a write signal on a write word line to write data from write bit lines into the latch, and a separate read port operable in response to a read signal on a read word line to read data from the latch to a read bit line. The circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory (where the voltage bounce arises from a simultaneous write to another memory cell in a same row).

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New Delhi, India

Hiten Advani