Intel Corporation

Mcafee, Inc.

Hisham Shafi

Mohan J Kumar

Theodros Yigzaw

Michael Mishaeli

Ganapati Srinivasa

Jason W Brandt

Ron Gabor

Ashok Raj

Shlomo Raikin

Ittai Anati

Jose Andy Vargas

Julius Yuli Mandelblat

Geeyarpuram N Santhanakrishnan

Gilbert A Neiger

Zeev Sperber

Vedvyas Shanbhogue

Gideon Gerzon

Ehud Cohen

Sergiu D Ghetie

Bret L Toll

Eliezer Weissmann

Rajesh M Sankaran

Andrew J Herdrich

Alon Naveh

Inder M Sodhi

Dheeraj R Subbareddy

Eugene Gorbatov

Stephen Anthony Fischer

David A Koufaty

Lihu Rappoport

Sarathy Jayakumar

Ashish V Choubal

Andrew D Henroid

Larisa Novakovsky

Scott D Hahn

Paolo L Narvaez

Rinat Rappoport

Neeraj S Upasani

Gaurav Khanna

Mishali Naik

Paul Brett

Gur Hildesheim

Abirami Prabhakaran

Oron Lenz

Sanjeev S Sahagirdar

Sameer Desai

Ravi L Sahita

Uday R Savagaonkar

Carlos V Rozas

Francis X Mckeen

Geoffrey S Strongin

Alexander Gendler

Nadav Shulman

Joseph Nuzman

Russell Jerome Fenger

Michael A Goldsmith

Robert S Chappell

Asit K Mallick

Tsvika Kurts

Kevin Safford

Ofer Levy

Deepak K Gupta

Jared Warner Stark, Iv

Yoni Aizik

Rodrigo Branco

Yuriy Bulygin

Scott P Bobholz

Hermann Gartler

Oded Lempel

Alex Berenzon

Ariel Berkovits

Chen Koren

James A Coleman

Vivekananthan Sanjeepan

Reouven Elbaz

Wojciech S Powiertowski

Sagar V Dalvi

Andrew A Furtak

Iris Sorani

Ariel Sabba

Ki W Yoon

Michael J St Clair

Oleksandr Bazhaniuk

Scott J Cape

William Penner

Shani Rehana

Yair Berger

Jonathan Mark Lutz

Gilad Holzstein

Dewan Prashant

Yogesh Bijlani

Russel J Fenger

Mikhail V Gorobets

Processors, methods, and systems for user-level interprocessor interrupts are described. In an embodiment, a processing system includes a memory and a processing core. The memory is to store an interrupt control data structure associated with a first application being executed by the processing system. The processing core includes an instruction decoder to decode a first instruction, invoked by a second application, to send an interprocessor interrupt to the first application; and, in response to the decoded instruction, is to determine that an identifier of the interprocessor interrupt matches a notification interrupt vector associated with the first application; set, in the interrupt control data structure, a pending interrupt flag corresponding to an identifier of the interprocessor interrupt; and invoke an interrupt handler for the interprocessor interrupt identified by the interrupt control data structure.

User-level interprocessor interrupts

Embodiments of apparatuses, methods, and systems for virtualization of interprocessor interrupts are disclosed. In an embodiment, an apparatus includes a plurality of processor cores; an interrupt controller register; and logic to, in response to a write from a virtual machine to the interrupt controller register, record an interprocessor interrupt in a first data structure configured by a virtual machine monitor and send a notification of the interprocessor interrupt to at least one of the plurality of processor cores.

Virtualization of interprocessor interrupts

An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Apparatus and method for detecting and recovering from data fetch errors

Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.

Apparatuses and methods for speculative execution side channel mitigation

Systems, methods, and apparatuses relating to processor non-write-back capabilities are described. In one embodiment, a processor includes a plurality of logical processors, a control register comprising a non-write-back lock disable bit, a cache shared by the plurality of logical processors, a bus to couple the cache to a memory to service a memory request for the memory from the plurality of logical processors, and a memory controller to disable a non-write-back lock access of the bus for a read-modify-write type of the memory request issued by a logical processor of the plurality of logical processors when the non-write-back lock disable bit is set to a first value, and implement the non-write-back lock access of the bus for the read-modify-write type of the memory request when the non-write-back lock disable bit is set to a second value.

Apparatuses, methods, and systems for processor non-write-back capabilities

A processor or system includes a processor core to execute a set of instructions to determine that a memory encryption mode is enabled. The memory encryption mode is to cause data stored to memory to be encrypted and data retrieved from the memory to be decrypted. The processor core is further to determine that a debug mode has been enabled and, responsive to a determination that the debug mode has been enabled, generate a second encryption key different than a first encryption key employed before reboot of a computing system. The processor core is further to transmit the second encryption key to a cryptographic engine for use in encryption and decryption of the data according to the memory encryption mode.

Preventing unauthorized access to encrypted memory

A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.

Read from memory instructions, processors, methods, and systems, that do not take exception on defective data

Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.

Supporting hang detection and data recovery in microprocessor systems

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Method for booting a heterogeneous system and presenting a symmetric core view

In an embodiment, a processor for Return Oriented Programming (ROP) detection includes at least one execution unit; a plurality of event counters, each event counter associated with a unique type of a plurality of types of control transfer events; and a ROP detection unit. The ROP detection unit may be to: adjust a first event counter in response to detection of a first type of control transfer events; in response to a determination that the first event counter exceeds a first threshold, access a first configuration register associated with the first event counter to read configuration data; identify a set of ROP heuristic checks based on the configuration data read from the first configuration register; and perform each ROP heuristic check of the identified set of ROP heuristic checks. Other embodiments are described and claimed.

Detection of return oriented programming attacks in a processor

Methods and apparatuses relating to a hardware memory test unit to check a section of a data storage device for a transient fault before the data is stored in and/or loaded from the section of the data storage device are described. In one embodiment, an integrated circuit includes a hardware processor to operate on data in a section of a data storage device, and a memory test unit to check the section of the data storage device for a transient fault before the data is stored in the section of the data storage device, wherein the transient fault is to cause a machine check exception if accessed by the hardware processor.

Hardware apparatuses and methods to check data storage devices for transient faults

In one embodiment, a processor includes a core having a fetch unit to fetch instructions, a decode unit to decode the instructions, and one or more execution units to execute the instructions. The core may further include: a first pair of block address range registers to store a start location and an end location of a block range within a non-volatile block storage coupled to the processor; and a block status storage to store an error indicator responsive to an occurrence of an error within the block range during a block operation. Other embodiments are described and claimed.

Interfacing with block-based storage in a processor

Growing community of inventors

Akko, Israel

Hisham Shafi