Intel Corporation

Hisham Abu Salah

Eliezer Weissmann

Efraim Rotem

Yoni Aizik

Doron Rajwan

Nadav Shulman

Nir Rosenzweig

Paul S Diefenbaugh

Guy M Therien

Russell Jerome Fenger

Yevgeni Sabin

Gal Leibovich

Esfir Natanzon

Daniel D Lederman

Barnes Cooper

Alon Naveh

Alexander Gendler

Michael Mishaeli

Deepak Samuel Kirubakaran

Jay D Schwartz

Arik Gihon

Monica Gupta

Ariel Gur

Ido Melamed

Niv Tokman

Guy Satat

Shay Levy

Evgeny Bolotin

Sharad C Tripathi

Avinash N Ananthakrishnan

Eugene Gorbatov

Dan Baum

Asit K Mallick

Rajshree Chabukswar

Israel Hirsh

Vijay Dhanraj

Arjan Van De Ven

Srinivas Pandruvada

Balaji Masanamuthu Chinnathurai

Guruprasad Settuvalli

Rafal J Wysocki

Srividya Ambale

Sumant Tapas

Meghana Gudaram

Raj Kumar Subramaniam

Arthur Leonard Brown

Eliezer Weissman

Jun Pan

Rajshree Arun Chabukswar

Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

Apparatuses, methods, and systems for hardware control of processor performance levels

In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.

System, apparatus and method for responsive autonomous hardware performance state control of a processor

A data processing system comprises a hybrid processor comprising a big TPU and a small TPU. At least one of the TPUs comprises an LP of a processing core that supports SMT. The hybrid processor further comprises hardware feedback circuitry. A machine-readable medium in the data processing system comprises instructions which, when executed, enable an OS in the data processing system to collect (a) processor topology data from the hybrid processor and (b) hardware feedback for at least one of the TPUs from the hardware feedback circuitry. The instructions also enable the OS to respond to a determination that a thread is ready to be scheduled by utilizing (a) an OP setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread. Other embodiments are described and claimed.

Technology for optimizing hybrid processor utilization

In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.

Utilization metrics for processing engines

Technologies are provided in embodiments to dynamically bias performance of logical processors in a core of a processor. One embodiment includes identifying a first logical processor associated with a first thread of an application and a second logical processor associated with a second thread, obtaining first and second thread preference indicators associated with the first and second threads, respectively, computing a first relative performance bias value for the first logical processor based, at least in part, on a relativeness of the first and second thread preference indicators, and adjusting a performance bias of the first logical processor based on the first relative performance bias value. Embodiments can further include increasing the performance bias of the first logical processor based, at least in part, on the first relative performance bias value indicating a first performance preference that is higher than a second performance preference.

Dynamic performance biasing in a processor

In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.

Controlling performance states of processing engines of a processor

In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

Forcing a processor into a low power state

In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.

Controlling forced idle state operation in a processor

Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.

Enhancing power-performance efficiency in a computer system when bursts of activity occurs when operating in low power

Interconnect frequency control technologies of adjusting an operating frequency of a communication interconnect between an integrated circuit comprising multiple functional hardware units are described. A power management unit (PMU) is configured to collect workload data from the functional hardware units and determine a workload metric from the workload data. The PMU adjusts an operating frequency of the communication interconnect in view of the workload metric.

Internal communication interconnect scalability

Growing community of inventors

Majdal Shams, Israel

Hisham Abu Salah