Hitachi, Ltd.

Renesas Electronics Corporation

Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Hisayuki Kato

Keiichi Yoshizumi

Kiyoshi Ogata

Kazuhiko Horikoshi

Kazufumi Suenaga

Asao Nishimura

Shuji Ikeda

Hideo Miura

Atsuyoshi Koike

Hisahiko Abe

Shunji Moribe

Jun Tanaka

Masahito Yamazaki

Shigeki Obayashi

Takeshi Iwamoto

Kazushi Kono

Toshiaki Yonezu

Shinji Nishihara

Yoshihiko Kusakabe

First protective films are formed to cover side surfaces of gate electrode portions. In an nMOS region, an extention implantation region is formed by causing a portion of the first protective film located on the side surface of the gate electrode portion to function as an offset spacer and using the offset spacer as a mask, and then, cleaning is done. Since silicon nitride films are formed on surfaces of the first protective films, the resistance to chemical solutions is improved. Furthermore, second protective films are formed on the first protective films, respectively. In a pMOS region, an extention implantation region is formed by causing a portion of the first protective film and a portion of the second protective film located on the side surface of the gate electrode portion to function as an offset spacer and using the offset spacer as the mask, and then, cleaning is done.

Semiconductor device and method for manufacturing the same

The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered. A plurality of projecting portionsare formed in the position shifted from the middle position of electric fuse part, and, more concretely, are formed in the position distant from viaand near via. A plurality of projecting portionsare formed in the position shifted from the middle position of electric fuse part, and, more concretely, are formed in the position distant from viaand near. That is, projecting portionsand projecting portionsare arranged in the shape of zigzag.

Semiconductor device

The present invention is a high quality semiconductor memory device using a ferroelectric thin film capacitor as a memory capacitor at a high manufacturing yield, the ferroelectric thin film of the capacitor is specified such that the relative standard deviation of crystal grain sizes is 13% or less, to thereby ensure a high remanent polarization value and a small film fatigue (large rewritable number).

Semiconductor memory device and manufacturing method thereof

A long life ferroelectric memory device using a thin ferroelectric film capacitor as a memory capacitor is obtained by disposing a plurality of degradation preventive layers on an upper protection electrode and an upper electrodeand a degradation preventive layer at the boundary of ferroelectric layer/electrodes, or providing a step of decreasing a modified layer at the boundary of ferroelectric layer/upper electrode. This provides a thin ferroelectric film capacitor which is subjected to less fatigue and imprinting and which has less degradation of ferroelectric characteristic to attain a long life ferroelectric memory device.

Ferroelectric memory device including an upper protection electrode

Along life ferroelectric memory device using a thin ferroelectric film capacitor as a memory capacitor is obtained by disposing a plurality of degradation preventive layers on an upper protection electrode and an upper electrode and a degradation preventive layer at the boundary of ferroelectric layer /electrodes or providing a step of decreasing a modified layer at the boundary of ferroelectric layer /upper electrode . This provides a thin ferroelectric film capacitor which is subjected to less fatigue and imprinting and which has less degradation of ferroelectric characteristic to attain a long life ferroelectric memory device.

Method of manufacturing a ferroelectric memory device

The present invention is a high quality semiconductor memory device using a ferroelectric thin film capacitor as a memory capacitor at a high manufacturing yield, the ferroelectric thin film of the capacitor is specified such that the relative standard deviation of a crystal grain sizes is 13% or less, to thereby ensure a high remanent polarization value and a small film fatigue (large rewritable number).

Semiconductor memory device having ferroelectric film and manufacturing method thereof

A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

Process for producing semiconductor device having crystallized film formed from deposited amorphous film

A gate oxide film and a gate electrode are formed on a surface of a P-type substrate . A concave portion is provided in a region of the P-type substrate , the region being contiguous to the gate electrode . On the P-type substrate , an N-type drain region is disposed on the opposite side of the gate electrode from the concave portion . N-type impurities are implanted into the P-type substrate at a predetermined angle relative to the latter, thereby forming an N-type region which includes a region underneath the concave portion and which is partially submerged beneath the gate oxide film . P-type impurities are then implanted into the P-type substrate at right angles to the latter, thus forming a P-type region which includes a region underneath the concave portion while covering the N-type region and which forms a PN junction diode in combination with the N-type region

Semiconductor device and method of manufacturing the same

In order to improve the dielectric constant, residual dielectric polarization, hysteresis characteristics, etc. of a high-dielectric or ferroelectric thin film for use in the formation of capacitive insulating films of capacitors of a DRAM or a ferroelectric RAM, a target having a density of at least 90% of the theoretical value is used in forming, by sputtering, a high-dielectric or ferroelectric thin film for use in the formation of capacitive insulating films of capacitors of a DRAM or a ferroelectric RAM.

Process for producing semiconductor integrated circuit device

A long life ferroelectric memory device using a thin ferroelectric film capacitor as a memory capacitor is obtained by disposing one or a plurality of degradation preventive layers on an upper protection electrode and an upper electrode,and a degradation preventive layer at the boundary of ferroelectric layer,/electrodes,, or providing a step of decreasing a modified layer at the boundary of ferroelectric layer,/upper electrode,. This provides a thin ferroelectric film capacitor which is subjected to less fatigue and imprinting and which has less degradation of the ferroelectric characteristic, thereby to attain a long life ferroelectric memory device.

Ferroelectric memory device and method for manufacturing the same

A gate oxide film,and a gate electrode,are formed on a surface of a P-type substrate,. A concave portion,is provided in a region of the P-type substrate,, the region being contiguous to the gate electrode,. On the P-type substrate,, an N-type drain region,is disposed on the opposite side of the gate electrode,from the concave portion,. N-type impurities are implanted into the P-type substrate,at a predetermined angle relative to the latter, thereby forming an N-type region,which includes a region underneath the concave portion,and which is partially submerged beneath the gate oxide film,. P-type impurities are then implanted into the P-type substrate,at right angles to the latter, thus forming a P-type region,which includes a region underneath the concave portion,while covering the N-type region,and which forms a PN junction diode in combination with the N-type region

Growing community of inventors

Kokubunji, Japan

Hisayuki Kato