Fujitsu Corporation

Hisayoshi Ohba

Jun Watanabe

Hideaki Yamauchi

Kenji Hashimoto

A method and computer program for generating a capacitance value rule table, which simplifies generation of the capacitance value rule table for multilayer wiring having a complex dielectric constant structure are provided. In the method, construction data of wire adjacent to a wire of interest is extracted (S), a common dielectric constant for a plurality of insulating film in the construction data is calculated (S), and capacitance value rule table (F) is created based on the common dielectric constant (s).

Method of generating capacitance value rule table for extraction of wiring capacitance and capacitance value rule table generation program

A method and program for capacitance extraction enabling reduction of the need for division into segments during extraction of capacitances in an LSI device having diagonal wires, so that increases in the number of processes for capacitance extraction can be suppressed are provided. In the method and program, a wire model is generated in which, for a wire segment such that the wire of interest and an adjacent wire are not parallel, either the wire of interest or the adjacent wire is replaced so as to be parallel to the other, and the capacitance of the wire of interest is extracted for this wire model, so that the number of processes in the capacitance extraction process can be reduced.

Method of extraction of wire capacitances in LSI device having diagonal wires and extraction program for same

A method for designing a semiconductor device in which dummy pattern density and design pattern density are equalized on the entire semiconductor chip. A layout pattern for a layout layer in a semiconductor device is divided into divided areas (step S1). A dummy pattern is inserted between design patterns in the divided areas obtained by dividing the layout pattern (step S2). Dummy pattern density and design pattern density in each divided area are calculated (step S3). Pattern rules for a dummy pattern in each divided area are changed so that the dummy pattern density and the design pattern density will be desired values (step S4).

Method, program, and apparatus for designing a semiconductor device

A semiconductor-device design method considering change in capacitance between wiring patterns due to an inserted dummy pattern. An information reception part receives dummy rule information about rules for dummy patterns and process information about wiring structure of wiring patterns. A capacitance calculation part calculates a capacitance value for each of wiring distances between the wiring patterns defined by the process information, under the condition that a dummy pattern defined by the dummy rule information is inserted between the wiring patterns. A wiring-pattern capacitance calculation part calculates capacitance values between wiring patterns of an intended semiconductor device defined by layout data stored in a layout database, referring to the capacitance values calculated by the capacitance calculation part. Thus, a semiconductor device considering change in capacitance between wiring patterns due to an inserted dummy pattern is designed.

Semiconductor-device design method, semiconductor-device design program and semiconductor-device design apparatus

In the present invention, conductive dummy patterns continuous in a direction perpendicular to adjacent wiring patterns are inserted at a first distance from the adjacent wiring patterns between the adjacent wiring patterns extending in one direction, in an interconnection wiring layer in an LSI. The insertion of such dummy patterns makes it possible to suppress variations in the degree of pattern density in the interconnection wiring layer and suppress variations in the pattern width in the etching process. Furthermore, since the conductive dummy patterns are continuous in the direction perpendicular to the adjacent wiring patterns, the values of capacitance between the adjacent wiring patterns in the same wiring layer assume a constant value corresponding to the first distance, regardless of the distance between the adjacent wiring patterns.

LSI design method having dummy pattern generation process and LCR extraction process and computer program therefor

A semiconductor device includes a real pattern and dummy patterns in respective different coordinate systems. Using a dummy pattern in a single coordinate system does not allow an effective dummy pattern arrangement. To the contrary, if the dummy patterns in different coordinate systems are used, minimum interval requirements may be satisfied in one coordinate system while such requirements are not met in another coordinate system.

Semiconductor device having dummy pattern

The present invention relates to an LCR extraction method for extracting LCR values from layout data having wiring pattern data in a plurality of wiring layers. The method has the steps of: generating the LCR values, for a wiring pattern, based on the layout data; finding the pattern congestion level in an area of the wiring pattern; and correcting the LCR values, based on pattern fluctuation values depending on the pattern interval between the wiring pattern and an adjacent pattern. Pattern width fluctuations occur in manufacturing processes in conjunction with the finer miniaturization of layout data, wherefore the precision of extracted LCR values can be enhanced by subjecting the LCR values found from layout data to corrections corresponding to those pattern width fluctuations.

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Kawasaki, Japan

Hisayoshi Ohba