Fujitsu Corporation

Fujitsu Microelectronics Limited

Hisayoshi Oba

Noboru Yokota

Noboru Kosugi

Munehiro Tahara

Kenichi Ushiyama

A method for a computer setting up a terminal layer of a semiconductor circuit having plural wiring layers including obtaining various kinds of information such as placement information relating to a plurality of cells or macros of the semiconductor circuit and being mounted onto a circuit board from a storage unit of the computer; comparing a driving capacity of a subject cell or macro, which is contained in the obtained information, and a resistance of wiring for connecting the subject cell or macro with the cell or macro at a connecting destination; and setting up a terminal layer based on a result of the comparing.

Method, storage media storing program, and component for avoiding increase in delay time in semiconductor circuit having plural wiring layers

A timing analysis apparatus includes a data extracting unit that extracts objective circuit data concerning an objective circuit to become an objective of a timing analysis from layout data indicating circuits on a large-scale-integration chip; a time calculating unit that calculates a delay time of the objective circuit based on the objective circuit data; a parameter calculating unit that calculates a parameter indicating a size of an arrangement area of the objective circuit based on the objective circuit data; an information calculating unit that calculates variation information concerning a variation of the delay time; and a timing analyzing unit that performs the timing analysis of the objective circuit using the delay time and the variation information.

Timing analysis apparatus, timing analysis method, and computer product

A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S); a mask with a modified pattern is prepared (S); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S).

Semiconductor device having embedded array

A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S ); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S ); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S ); a mask with a modified pattern is prepared (S ); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S ).

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Kawasaki, Japan

Hisayoshi Oba