Other

Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Ryoden Semiconductor System Engineering Corporation

Hisayoshi Hanai

Teruhiko Funakura

Hisaya Mori

Shinji Yamada

Yasuhiro Mabuchi

Masatoshi Maga

Takato Inoue

An apparatus for testing a semiconductor integrated circuit has a test circuit board and an ancillary test device. The ancillary test device can test a digital circuit. The ancillary test device has test pattern memory, a test pattern signal generator, and a control section for controlling an operation for the test pattern data selected from among the plurality of test pattern data sets stored in the test pattern memory and an operation for writing the selected test pattern data into the test pattern signal generator. The ancillary test device generates a test input pattern signal on the basis of test pattern data written in the test pattern signal generator and determines a test output pattern signal output from the semiconductor integrated circuit on the basis of the test input pattern signal, thereby testing a digital circuit.

Apparatus for testing semiconductor integrated circuit

A jitter measurement circuit includes: a conversion section sampling one of a reference signal and a measurement target signal in response to the other of the signals, thereby obtaining a sampling data string; and a determination section measuring jitter of the measurement target signal on the basis of the sampling data string obtained by the conversion section. Since the reference signal is a stable signal having a predetermined cycle, the sampling data string as a measurement result depends on the measurement target signal. Therefore, it is possible to simply measure jitter level in accordance with irregularity of the measurement result and on the basis of relative measurement to expected value data.

Jitter measurement circuit for measuring jitter of measurement target signal on the basis of sampling data string obtained by using ideal cyclic signal

A test-assisting device (BOST device) is provided in the vicinity of a testing circuit board that transmits signals to and receive signals from a semiconductor integrated circuit to be tested, and the D/A converter circuit for testing, the A/D converter circuit for testing, the measured-data memory, and the analyzing portion of the test-assisting device are carried by separate circuit boards.

Tester for semiconductor integrated circuits

A low-cost semiconductor tester which saves memory space for storing a test pattern by means of producing a high-speed clock while preparing a test pattern at a low-speed test cycle and which has a test-pattern storage circuit of small storage capacity, as well as a semiconductor test method using the semiconductor tester. The semiconductor tester includes a reference-signal-generation circuit for producing a test cycle to be taken as a reference-signal, a waveform formation circuit for producing the geometry of an output waveform on the basis of the test cycle, and a waveform output circuit which sets the voltage of the geometry of the output waveform and applies the voltage to a semiconductor element to be measured. A ring oscillation circuit is provided in the waveform formation circuit and has a variable delay circuit. The ring oscillation circuit converts the output waveform, which waveform is produced at a predetermined timing, into a high-speed clock waveform.

Semiconductor tester, and method of testing semiconductor using the same

A memory tester including an algorithmic pattern generator (ALPG) for generating a test pattern as a digital signal based on vector data is provided with a digital-to-analog converter built in the memory tester or provided outside the memory tester. Thus, the function of a device under test (DUT) having the analog-to-digital converting function can be verified. In other words, an address signal included in the test pattern generated in the ALPG is used for generating an analog signal to be input to the DUT having the analog-to-digital converting function, not for address designation. A control unit compares an output digital signal generated in the DUT with the address signal generated in the ALPG as a test digital signal to detect the degree of agreement between these signals, thereby verifying the analog-to-digital converting function of the DUT. Consequently, a test system and a testing method capable of testing the analog-to-digital or digital-to-analog converting function of the DUT using the memory tester are obtained.

Growing community of inventors

Tokyo, Japan

Hisayoshi Hanai