Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Hisaya Kato

Takaaki Konishi

Kazuya Ueda

Hiroaki Ozeki

Naoya Tokunaga

Hiroshi Azakami

Kunio Ninomiya

Seiji Sakashita

Ippei Kanno

Sadashi Kageyama

Takeo Yasuho

Kazuaki Suzuki

Toshiyuki Satomi

Mikihiro Ouchi

A first switching circuit () outputs a first radio signal representing a plurality of time-division multiplexed programs and a second radio signal other than the first radio signal, one at a time according to a switching signal. A voltage control oscillator () outputs a local signal at a frequency suitable for whichever signal outputted. Using the local signal generated, a frequency converter () frequency converts the first and second radio signals to first and second baseband signals, respectively. Via a second switching circuit (), a first baseband unit () and a second baseband unit () are supplied with the first and second baseband signals, respectively, and demodulate them to first and second data signals. A switching unit () supplies the switching signal indicating periods during which the first radio signal represents a user-selected program, to a tuner unit () where the first and second radio signals are processed by time-sharing.

Wireless terminal device

A digital broadcast receiving apparatus, which has a receiving circuit for receiving a transmitted high frequency signal of a plurality of time division multiplexed programs, includes a circuit for selecting a better receiving characteristic condition while a desired program is not received.

Digital broadcast receiving apparatus

A synchronization error occurs when a DTV signal is distorted on a transmission path and this deteriorates demodulation capability. The digital demodulation device and the synchronization detecting method of the invention can correct the synchronization position when determining that a synchronization error has occurred. A controller receives a center tap coefficient, for example, from a waveform equalizer and compares the coefficient with a given center tap coefficient threshold. If the coefficient is smaller than the threshold, the controller determines that a synchronization detector has made a synchronization error and outputs a control signal. The synchronization detector receiving the control signal re-detects a sync signal included in a received signal, to detect a new correct sync signal and thus correct the synchronization error.

Digital demodulation device and synchronization detecting method

An OFDM baseband signal that has undergone a synchronization carrier modulation or a differential carrier modulation is inputted to a complex signal converter for nonlinear distortion equalization so as to be converted according to the N-th order function conversion characteristics (N&#x3e;1). Then, nonlinear distortion in the OFDM baseband signal is compensated for. At this time, the following is used as a conversion equation:()=()+&#x3a3;()()(&#x3e;1)wherein the values of the input signal, the output signal and the coefficient for m-th order distortion equalization at time n are, respectively, x(n), y(n) and a(n).

Front end processor for data receiver and nonlinear distortion equalization method

An input signal DT contains a segment synchronization signal compliant with the ATSC standard. A clock multiplication sectionmultiplies a clock CK. A switchable sampling sectionselects a sample point from among a plurality of timing points that are defined by the multiplied clock, and samples the input signal DT at the selected sample point. Moreover, the switchable sampling sectionswitches sample points from one to another in a synchronization-unestablished state. Once the segment synchronization is established, a synchronization detection device may maintain a synchronization-established state until the field synchronization detection fails, or the synchronization detection device may output a synchronization detection signal after shifting it in the time direction based on a bit error rate RT of the input signal.

Synchronization detection apparatus

A digital demodulation apparatus automatically controls gain based on a state of receiving a digital modulated signal. The digital demodulation apparatus amplifies a digital modulated signal wave received through the air with the gain automatically controlled so as to have a predetermined amplitude. In the digital demodulation apparatus, a receive level variation detector detects receive level variation, an amount of noise components of the received digital signal wave. A gain controllercontrols the gain with a receive level variation adaptive control signal based on the detected receive level variation, the amount of noise components.

Automatic gain control for digital demodulation apparatus

To present a digital broadcast demodulator, in a demodulator of digital terrestrial wave broadcast for transmitting coded digital video and audio information in a packet form, capable of detecting packet synchronism stably and precisely, controlling the AGC, and processing the clock regeneration, in spite of inferior environments for receiving broadcast, such as deterioration of C/N of signal due to weak electric field, or strong ghost or multipath characteristic of terrestrial waves.

Demodulator for demodulating digital broadcast signals

In an automatic gain control amplifier, an RF automatic gain controller controls the gain of a radio frequency signal. A frequency converter frequency-converts the radio frequency signal into an intermediate frequency signal. An IF automatic gain controller controls the gain of the intermediate frequency. A level detector detects a signal level of the gain-controlled intermediate frequency signal, and generates a level signal. An automatic gain control signal generator separately controls, based the level signal, the RF automatic gain controller and the IF automatic gain controller.

Automatic gain control apparatus

In a clock recovery circuit for DTV using a VSB modulation method, if the frequency of the symbol clock is fs, since the frequency difference between the fs/2 component signal of the VSB signal and the pilot signal is constant at fs/2, it is possible accurately to detect the phase error from their differential signal. Furthermore there is no distortion of the clock signal frequency of the VSB signal, even when the symbol data is distorted by multi-pass distortion or the like, since clock signal regeneration is performed by frequency domain processing. By employing this type of principle and performing phase error detection for each symbol at a time, it is possible to ensure a high speed tracking performance for clock signal regeneration.

Clock recovery circuit

A broadcast receiving apparatus provides multifunctionality to cope with analog modulated input signals as well as digital input signals modulated by various types of modulation schemes. The apparatus comprises a detector for detecting the modulation scheme of input signals, and a switch for switching one or more of the characteristic of a filtering section, an amplifying section, and a detection section, depending upon the detected modulated scheme.

Broadcast receiving apparatus

A Vestigal Sideband (VSB) demodulator having a clock generator for generating a clock signal based on a symbol frequency of the VSB signal; an A/D converter for converting the VSB signal into a digital signal based on the clock signal of the clock generator; a first multiplier for multiplying the digital signal by a first value sequence and generating a first multiplier output signal; a second multiplier for multiplying the digital signal by a second value sequence and generating a second multiplier output signal; a complex type filter for shaping and VSB demodulation of the multiplier output signals and generating Inphase and Quadrature data output signals; a decimating circuit for decimating the Inphase and Quadrature data output signals and generating decimated signals; a complex multiplier for multiplying the decimated signals by a predetermined value and generating multiplied output signals; an error detector for detecting a frequency deviation and a phase deviation from the multiplied output signals and generating the predetermined value for the complex multiplier; and DC offset canceler for removing a DC component from a portion of the multiplied output signals of the complex multiplier.

Growing community of inventors

Soraku-gun, Japan

Hisaya Kato