Matsushita Electric Industrial Co., Ltd.

Matsushita Electronic Industrial Co., Ltd

Hisato Yoshida

Kimihiko Aiba

Katsuji Aoki

Masahiko Toyonaga

Hiroyuki Tsujikawa

Kenji Shimazaki

Masahiro Gion

Junichi Yano

Akihiko Ohtani

Junya Yamamoto

Michiaki Muraoka

Shouzou Hirano

Masanori Tsutsumi

Atsushi Ubukata

Katsuyuki Imamura

Yoshifumi Matsumoto

Junichi Mori

Akira Sota

Kaori Matsui

Ritsuko Kurazono

Yoichiro Mae

For detecting a failure of a logic circuitprovided in a semiconductor integrated circuit due to deterioration with age, or the like, there is provided a reference-producing circuitusing a logic different from the logic of the logic circuit. The reference-producing circuitproduces an abnormal/normal determination reference S for a predetermined output signal out output from the logic circuit. The reference-producing circuitis made from only a portion of the logic of the logic circuitor with a logic totally different from the logic of the logic circuitto produce the determination reference S, so that the circuit scale of the reference-producing circuitis smaller than that of the logic circuit. The determination reference S from the reference-producing circuitand the output signal out from the logic circuitare compared with each other by a determination circuit

Semiconductor integrated circuit, and semiconductor system including that semiconductor integrated circuit

A semiconductor integrated circuits can send and receive signals to and form a configuration memory. The semiconductor integrated circuits is provided therein wiht an instruction memory, an instruction storage portion that stores reserved instructions as F instructions, and stores the substantially equivalent processing contents to the F instructions as substitute instructions for processing by the CPU, a pre-fetch portion, a history storage portion, a diagnosing portion for diagnosing the types of instructions, a reprogramming control portion for reprogramming the instructions, a CPU, an FPGA, a configuration data memory, a built-in memory, and a configuration data tag. When the configuration data of the F instruction does not exist in the FPGA, the substantially equivalent processing by FPGA is executed by the CPU by making use of the substitute instructions.

Integrated circuit with CPU and FPGA for reserved instructions execution with configuration diagnosis

An electromagnetic disturbance analysis method for analyzing an external noise to a semiconductor integrated circuit includes an impedance extraction step of extracting impedance information on the power wiring in the target semiconductor integrated circuit or the power wiring in the semiconductor integrated circuit and the external power wiring of the semiconductor integrated circuit, an equivalent circuit creating step of creating an equivalent circuit from the impedance information, and an analysis step of supplying a noise waveform externally and analyzing the influence of the noise on the semiconductor integrated circuit.

Electromagnetic disturbance analysis method and apparatus and semiconductor device manufacturing method using the method

There is provided a correlation degree operation apparatus in which the search area is readily extensible, in which a high-speed process can be assured even though the search area is extended, and which can be formed in a simple arrangement. The search area memory stores the picture element data of a search area including ((m.times.M).times.L) candidate blocks. The correlation degree operation unit executes an operation of a degree of correlation between a reference picture block and each of the candidate blocks, with the use of picture element data supplied from the search area memory, this operation being executed by a pipeline process for each candidate block group composed of (M.times.L) candidate blocks. The search area memory has the function of supplying four picture element data at the same clock cycle. This enables the correlation degree operation unit to continuously execute the pipeline processes for the candidate block groups. It is therefore possible to continuously execute the operations of correlation degree between the reference picture block having (M.times.N) picture elements and ((m.times.M).times.L) candidate blocks.

Correlation degree operation apparatus, parallel correlation degree

A layout area includes a clock interconnection consisting of an upward interconnection and a downward interconnection. The upward interconnection extends from the output terminal of a clock buffer which receives an external clock signal to a turning point while passing along the vicinity of a plurality of flip-flops. The downward interconnection extends from the turning point to a free end, reversing along the upward interconnection. Clock branch circuits are provided in the vicinity of the flip-flops. The clock branch circuits have a function of letting a third clock signal make a transition when the sum of the time integral of a first clock signal on the upward interconnection and the time integral of a second clock signal on the downward interconnection has become equal to the time integral for one pulse of one of the first clock signal and the second clock signal.

Clock distribution circuit with clock branch circuits connected to

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Nara, Japan

Hisato Yoshida