Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Hisataka Meguro

Satoshi Nagashima

Fumitaka Arai

Kenji Aoyama

Ryota Katsumata

Riichiro Shirota

Yoshio Ozawa

Takashi Shimizu

Ichiro Mizushima

Takashi Suzuki

Toshitake Yaegashi

Katsuyuki Sekine

Takashi Fukushima

Masahiro Kiyotoshi

Hajime Nagano

Masayuki Ichige

Yasuhiko Matsunaga

Hiroaki Tsunoda

Hideto Takekida

Minori Kajimoto

Akira Shimizu

Keisuke Kikutani

Masahisa Sonoda

Shigeki Sugimoto

Hideyuki Kinoshita

Shigeru Kinoshita

Shoichi Miyazaki

Kenta Yamada

Hidefumi Mukai

Takehiro Kondoh

Junya Fujita

Kenji Kawabata

Hideaki Masuda

Shinya Takahashi

Hideyuki Yamawaki

According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided above the foundation layer, a semiconductor body, and a charge storage portion. The stacked body includes a plurality of electrode layers stacked with an air gap interposed, a plurality of select gate layers stacked in a stacking direction of the electrode layers, and an insulating body provided between the select gate layers adjacent to each other in the stacking direction. The semiconductor body extends in the stacking direction in the stacked body. The charge storage portion is provided between the semiconductor body and one of the electrode layers.

Semiconductor device and method for manufacturing same

A method for manufacturing a semiconductor memory device includes forming a first insulating layer on a conductive layer; forming a second insulating layer on the first insulating layer, the second insulating layer including a first layer and a second layer having nitrogen and hydrogen bonds with higher density than a density thereof in the first layer; forming a third insulating layer on the second insulating layer; forming a semiconductor layer extending through the first insulating layer and the second insulating layer in a direction toward the third insulating layer from the conductive layer; selectively removing the second insulating layer to form a space, the first insulating layer being exposed in the space; forming the fourth insulating layer between the conductive layer and the first insulating layer, the fourth insulating layer being formed by thermally oxidizing the conductive layer through the first insulating layer in the space.

Semiconductor memory device and method for manufacturing same

A semiconductor memory device according to one embodiment includes a stacked body, a semiconductor pillar and a plurality of charge storage films. The stacked body includes a plurality of electrode films and air gaps. The plurality of electrode films are disposed to be separated from each other along a first direction. Each of the air gaps is made between the electrode films. The semiconductor pillar extends in the first direction and pierces the stacked body. The plurality of charge storage films are provided between the semiconductor pillar and the plurality of electrode films. The plurality of charge storage films are partitioned every electrode film.

A nonvolatile semiconductor memory device a first memory cell array layer, a first insulation layer formed on top of the first memory cell array layer, a second memory cell array layer formed on the first insulation layer, and a control gate. The first and second memory cell array layers have first and second NAND cell units provided with multiple first and second memory cells connected in series in a first direction and the first and second selection gates connected at both ends of the multiple first and second memory cells. The control gate is formed via an insulation layer between gates of the memory cells on both sides thereof in the first direction, and extends in the second direction perpendicular to the first direction.

Nonvolatile semiconductor device and its manufacturing method having memory cells with multiple layers

According to one embodiment, a method of manufacturing a device, includes forming a first core including a line portion extending between first and second regions and having a first width and a fringe having a dimension larger than the first width, forming a mask on the fringe and on a first sidewall on the first core, removing the first core so that a remaining portion having a dimension larger than the first width is formed below the mask, forming a second sidewall on a pattern corresponding the first sidewall and the remaining portion, the second sidewall having a second width less than the first width and facing a first interval less than the first width in the first region and facing a second interval larger than the first interval in the second region.

Method of manufacturing a memory device using fine patterning techniques

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor obtained by sequentially stacking the gate insulation film, the floating gate electrode, the interelectrode insulation film, and the control gate electrode over the channel semiconductor layer. The control gate electrode has a structure obtained by sequentially stacking the semiconductor film, the silicide phase-change suppressing layer, and the silicide film. In addition, the silicide phase-change suppressing layer includes a polycrystalline silicon film in which at least one of C, F, and N is doped in a concentration range of 1&#xd7;10to 5&#xd7;10[atom/cm].

Nonvolatile semiconductor memory device

Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.

Nonvolatile semiconductor memory device and method for manufacturing same

According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a tunneling insulating film, a floating gate, a leak suppression unit, an inter-gate insulating film, and a control gate. The substrate includes silicon. The tunneling insulating film is provided on the substrate. The floating gate is provided on the tunneling insulating film. The leak suppression unit is provided on the floating gate. The inter-gate insulating film is provided on the leak suppression unit. The control gate is provided on the inter-gate insulating film. The dielectric constant of the leak suppression unit is higher than a dielectric constant of the inter-gate insulating film.

Nonvolatile semiconductor memory device and method for manufacturing the same

A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other.

A semiconductor storage device includes: a substrate having a semiconductor layer at least on a surface thereof; and a plurality of quantum dot elements forming a charge storage layer formed above the semiconductor layer via a first insulating film that becomes a tunnel insulating film in such a manner that the quantum dot elements are connected with a bit line in series, wherein each quantum dot element forms a single electron memory.

Semiconductor storage device and manufacturing method thereof

A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.

Semiconductor storage device and method for manufacturing the same

In a method for manufacturing a non-volatile semiconductor device according to this invention, steps are provided for forming a plurality of first semiconductor portions over a substrate; selectively growing a plurality of second semiconductor portions in contacting with said plurality of first semiconductor portions respectively; partially removing said plurality of second semiconductor portions to prepare a plurality of floating gates with substantially flat surfaces; forming an insulating layer over said plurality of floating gates; and forming a control gate over said insulating layer.

Method of manufacturing non-volatile semiconductor memory

A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined.

Semiconductor device and method of manufacturing the same

Element isolation insulating layers have an STI structure, and their upper surfaces are flat. A floating gate electrode is formed in a recess which is formed by projections of the element isolation insulating layers. The two opposing side surfaces of the floating gate electrode are covered with the element isolation insulating layers. The upper surface of the floating gate electrode is substantially leveled with the upper surfaces of the element isolation insulating layers. A gate insulating layer is formed on the floating gate electrode and element isolation insulating layers. The underlayer of this gate insulating layer is flat. A control gate electrode is formed on the gate insulating layer.

Growing community of inventors

Yokkaichi, Japan

Hisataka Meguro