Fujitsu Corporation

Hisashige Ando

Takahiro Sakuraba

Michael C Shebanow

Michael Butler

Yoshitomo Ozeki

Takashi Takezono

Toshiaki Kitamura

Makoto Katsuyama

Saburo Sasanuma

To provide a floating point arithmetic circuit for efficiently defecting an error, which has a large numerical error, with a less circuit amount, the floating point arithmetic circuit comprises a first arithmetic unit for outputting a first arithmetic result, a second arithmetic unit for outputting a second arithmetic result, and a comparison circuit for making a comparison between the first and the second arithmetic results by a predetermined bit width.

Arithmetic circuit, arithmetic method, and information processing device

An information-processing device that executes a specific process more frequently than other processes among a variety of processes is provided. The information-processing device includes a first processor capable of executing an instruction set corresponding to the variety of processes, and a second processor capable of executing a portion of or the entire instruction set, the second processor being capable of executing a part of the instruction set corresponding to the specific process more efficiently than the first processor, wherein the second processor executes the specific process whereas the first processor executes the other processes. Accordingly, the information-processing device can execute a variety of instructions efficiently.

Information-processing device with transaction processor for executing subset of instruction set where if transaction processor cannot efficiently execute the instruction it is sent to general-purpose processor via interrupt

The present invention relates to a voltage stabilizer that stabilizes the voltage of a power supply line on a semiconductor substrate and is intended to provide a voltage stabilizer having a small mounting area on the semiconductor substrate, capable of stabilizing the voltage of the power supply path connecting the power supply and semiconductor substrate. The voltage stabilizer includes a monitoring sectionconnected to the power supply line Vdd that monitors the potential of the power supply line Vdd and outputs a monitor signal indicating the monitoring result and a first current control sectionthat passes a current from the power supply line Vdd according to the monitor signal to stabilize the voltage of the power supply line Vdd, capable of freely passing a current continuously.

Voltage stabilizer

Disclosed is a computer in which an error caused by an intermittent failure is corrected by using a misprediction recovery mechanism which performs recovery processing if, after having predicted a branch destination of a branch instruction and speculatively executed an instruction at the predicted branch destination, it turns out that the branch prediction was wrong. The computer includes an error detection mechanism for detecting an error in logic operation of the computer, and an instruction re-execution mechanism for correcting an error caused by an intermittent failure when an error is detected by the error detection mechanism, by restoring the computer, using the misprediction recovery mechanism, to a state that existed before the occurrence of the error, and by re-executing a sequence of instructions including the instruction where the error is detected.

Computer and error recovery method for the same

A multi-plane video RAM for displaying a color image on a display apparatus. A multi-plane bit operation unit is used for calculating input data from an external stage based on a predetermined rule corresponding to an information applied from the external stage. Memory arrays are operatively connected to the multi-plane bit operation unit for writing resultant data calculated by the multi-plane bit operation unit. Each array having three-dimensionally arranged k sets of memory planes each consisting of m (rows).times.n (columns); wherein the same corresponding positions of the k sets of memory planes are simultaneously accessed and the resultant data calculated by the multi-plane bit operation unit are also simultaneously written thereto.

Multi-plane video RAM

A vector pattern processing circuit for a bit map display system including a display unit having a plurality of quasi regions in a matrix form defined in a plane of the display unit each forming N.times.N dots. The circuit includes first and second memory units each including a plurality of words formed in a matrix, each word having an N.times.N bits structure; the words in the first memory unit corresponding to diagonal quasi regions of the display unit and the words in the second memory unit corresponding other diagonal quasi regions; first and second word register units, each having an N.times.N bits structure; a digital differential analyzer (DDA) generating a first dot data of a primary axis for a processing vector pattern and a second dot data of a subsidiary axis perpendicular to the primary axis in response to a gradient of the vector pattern along the primary axis for every N dots in the primary axis. The circuit further includes a bit setting circuit energizing one of the word register units in response to the first and second dot data from the DDA and setting a bit defined by the dot data to the energized word register unit in each dot data generation time at the DDA; and a store control circuit addressing at least one address of a word in one of the memory unit defined by the coordinate, so that at least one of data set in one of the word register units is stored in the word defined by the address.

Vector pattern processing circuit for bit map display system

A majority decision logic circuit has an odd number of elementary input signal circuits connected in parallel with a power source, each of the elementary input signal circuits being composed of a pair of P- and N-channel MOS transistors, the drains of the MOS transistors being interconnected to form an output terminal at the connection point and the gates being interconnected to form an input terminal at the connection point, all the output terminals of the elementary input signal circuits being connected together to form the output terminal of the majority decision logic circuit. A majority decision logic circuit has, in addition to the odd number of elementary input signal circuits, a plurality of logic circuits having their output terminals respectively connected to the input terminal of the elementary input signal circuits. A majority decision logic circuit comprises the elementary input signal circuits, the logic circuits and switching circuits, whereby the majority of outputs of a selected odd number of input signal circuits is decided. The abovesaid circuits can be formed with MOS transistors only, and are easily fabricated as an integrated circuit.

Majority decision logic circuit

An error correcting circuit utilizing a cube circuit for correcting errors in data having n+1 bits in accordance with the syndromes S.sub.1 and S.sub.3 from a check matrix H. The circuit comprises a generator for generating syndromes S.sub.1 and S.sub.3, means for providing (S.sub.1 -a.sub.i) based on the modulo 2 calculation for the i.sub.th line vector ##EQU1## OF THE CHECK MATRIX H corresponding to each data bit d.sub.1, means for multiplying (S.sub.1 -a.sub.i) three times, check means for checking the coincidence between (S.sub.1 -a.sub.i) and (S.sub.3 -a.sub.i.sup.3), and an inverting means for inverting the d.sub.i bit when the coincidence is detected. In the present invention, by utilizing a cube circuit the check circuit can be simplified.

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Kawasaki, Japan

Hisashige Ando