Sumitomo Chemical Company, Limited

University of California

National Institute of Advanced Industrial Science and Technology

The University of Tokyo

Sumika Epi Solution Company, Ltd.

Hisashi Yamada

Shuji Nakamura

Kenji Iso

Steven P DenBaars

James Stephen Speck

Noboru Fukuhara

Makoto Saito

Asako Hirai

Masahiko Hata

Zhongyuan Jia

Shinichi Takagi

Masafumi Yokoyama

Mitsuru Takenaka

Tetsuji Yasuda

Hisashi Masui

Yuji Urabe

Kenji Kasahara

Tomoyuki Takada

Hideki Takagi

Taro Itatani

Takenori Osada

Taiki Yamamoto

Noriyuki Miyata

Hiroyuki Ishii

Takeshi Aoki

SangHyeon Kim

Provided is a semiconductor wafer in which a nitride crystal layer on a silicon wafer includes a reaction suppressing layer to suppress reaction between a silicon atom and a Group-III atom, a stress generating layer to generate compressive stress and an active layer in which an electronic element is to be formed, the reaction suppressing layer, the stress generating layer and the active layer are arranged in an order of the reaction suppressing layer, the stress generating layer and the active layer with the reaction suppressing layer being positioned the closest to the silicon wafer, and the stress generating layer includes a first crystal layer having a bulk crystal lattice constant of al and a second crystal layer in contact with a surface of the first crystal layer that faces the active layer, where the second crystal layer has a bulk crystal lattice constant of a2 (a1&#x3c;a2).

Semiconductor wafer and method of inspecting semiconductor wafer

A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15&#xb0; or greater miscut angle towards the a-axis direction and a less than 30&#xb0; miscut angle towards the a-axis direction.

Planar nonpolar group-III nitride films grown on miscut substrates

A semiconductor substrate includes a substrate, an insulating layer, and a semiconductor layer. The insulating layer is over and in contact with the substrate. The insulating layer includes at least one of an amorphous metal oxide and an amorphous metal nitride. The semiconductor layer is over and in contact with the insulating layer. The semiconductor layer is formed by crystal growth.

Semiconductor substrate, field-effect transistor, integrated circuit, and method for fabricating semiconductor substrate

Provided is a semiconductor wafer including a base wafer, a first insulating layer, and a semiconductor layer. Here, the base wafer, the first insulating layer and the semiconductor layer are arranged in an order of the base wafer, the first insulating layer and the semiconductor layer, the first insulating layer is made of an amorphous metal oxide or an amorphous metal nitride, the semiconductor layer includes a first crystal layer and a second crystal layer, the first crystal layer and the second crystal layer are arranged in an order of the first crystal layer and the second crystal layer in such a manner that the first crystal layer is positioned closer to the base wafer, and the electron affinity Eof the first crystal layer is larger than the electron affinity Eof the second crystal layer.

Semiconductor wafer, field-effect transistor, method of producing semiconductor wafer, and method of producing field-effect transistor

Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of InGaAsP(0&#x3c;x1&#x2266;1, 0&#x2266;y1&#x2266;1), the second semiconductor crystal layer is made of InGaAsP(0&#x2266;x2&#x2266;1, 0&#x2266;y2&#x2266;1, y2&#x2260;y1), and the electron affinity Eof the first semiconductor crystal layer is lower than the electron affinity Eof the second semiconductor crystal layer.

Field-effect transistor, semiconductor wafer, method for producing field-effect transistor and method for producing semiconductor wafer

There is provided a method of producing a semiconductor wafer by thermally processing a base wafer having a portion to be thermally processed that is to be thermally processed. The method comprises a step of providing, on the base wafer, a portion to be heated that generates heat through absorption of an electromagnetic wave and selectively heats the portion to be thermally processed, a step of applying an electromagnetic wave to the base wafer, and a step of lowering the lattice defect density of the portion to be thermally processed, by means of the heat generated by the portion to be heated through the absorption of the electromagnetic wave.

Method for producing semiconductor substrate, semiconductor substrate, method for manufacturing electronic device, and reaction apparatus

A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an &#x3b1;-axis direction comprising a 0.15&#xb0; or greater miscut angle towards the &#x3b1;-axis direction and a less than 30&#xb0; miscut angle towards the &#x3b1;-axis direction.

A III-nitride film, grown on an m-plane substrate, includes multiple quantum wells (MQWs) with a barrier thickness of 27.5 nm or greater and a well thickness of 8 nm or greater. An emission wavelength can be controlled by selecting the barrier thickness of the MQWs. Device fabricated using the III-nitride film include nonpolar III-nitride light emitting diodes (LEDs) with a long wavelength emission.

Nonpolar III-nitride light emitting diodes with long wavelength emission

An off-axis cut of a nonpolar III-nitride wafer towards a polar (&#x2212;c) orientation results in higher polarization ratios for light emission than wafers without such off-axis cuts. A 5&#xb0; angle for an off-axis cut has been confirmed to provide the highest polarization ratio (0.9) than any other examined angles for off-axis cuts between 0&#xb0; and 27&#xb0;.

Enhancement of optical polarization of nitride light-emitting diodes by wafer off-axis cut

Planar nonpolar m-plane group III nitride films grown on miscut substrates

An increase in the Indium (In) content in light-emitting layers of light-emitting diode (LED) structures prepared on nonpolar III-nitride substrates result in higher polarization ratios for light emission than LED structures containing lesser In content. Polarization ratios should be higher than 0.7 at wavelengths longer than 470 nm.

Enhancement of optical polarization of nitride light-emitting diodes by increased indium incorporation

A thin-film crystal wafer having a pn junction includes a first crystal layer of p GaAs, a second crystal layer of n InAlGaP, the first and second crystal layers being lattice-matched layers that form a heterojunction, and a control layer of a thin-film of InAlGaP differing in composition from the n InAlGaP of the second crystal layer is formed at the interface of the heterojunction. The control layer enables the energy discontinuity at the interface of the InAlGaP/GaAs heterojunction to be set within a relatively broad range of values and thus enables the current amplification factor and the offset voltage to be matched to specification values by varying the energy band gap at the heterojunction.

Growing community of inventors

Tsukuba, Japan

Hisashi Yamada