Kabushiki Kaisha Toshiba

Hisashi Ueno

Mitsuo Isobe

Takayasu Sakurai

Kazutaka Nogami

Naokazu Miyawaki

Keiji Maruyama

Kazuhiro Sawada

Ryosuke Matsuo

Masaaki Kuwagata

Tatsuya Inatsuki

Makiji Kobayashi

A semiconductor integrated circuit includes a bias voltage regulation circuit having variable resistors which are provided between voltage output circuits of higher and lower potential sides and changes corresponding to a specified condition such as V.sub.CC and a temperature. The variable resistors and bias voltage output circuits form a V.sub.CC divider, and the variable resistors properly regulate a bias voltage supplied to an oscillation circuit corresponding to each of the specified conditions. Accordingly, if the oscillation circuit is used in an automatic refresh circuit of a PSRAM, an increase of a refresh operation frequency is suppressed regardless of an increase in V.sub.CC. Since a temperature depending variable resistor causes a resistance value to be reduced by the predetermined characteristics against the temperature increase, it is possible to set an oscillation frequency to provide a desired pause for guarantee of circuit operation. It is possible to provide a ring oscillator having a low dependency of the oscillation frequency on a power source voltage and a temperature characteristic, thereby decreasing its current consumption.

Semiconductor integrated circuit including ring oscillator of low

A refresh control circuit for a pseudo static random access memory includes a refresh control signal output circuit for outputting a refresh control signal to accomplish refresh control of the pseudo static random access memory, and includes a delay circuit. A first chip enable signal from a control device such as a MPU is delayed by the delay circuit and outputted as a second chip enable signal for the PSRAM. As the first chip enable signal level changes from a selection level to a non-selection level, the refresh control signal level changes to a non-refresh level. This state is maintained for a predetermined period. After the second chip enable signal changes from the selection level to the non-selection level, the refresh control signal returns from the non-refresh level to the refresh level. Thus, the PSRAM enters into the refresh state during the non-selection state, and is refreshed. This refresh operation is necessarily performed after an access to PSRAM.

Refresh control circuit of pseudo static random access memory and pseudo

A refresh control circuit for a pseudo static random access memory includes a refresh control signal output circuit for outputting a refresh control signal to accomplish refresh control of the pseudo static random access memory, and includes a delay circuit. A first chip enable signal from a control device such as a MPU is delayed by the delay circuit and outputted as a second chip enable signal for the PSRAM. As the first chip enable signal level changes from a selection level to a non-selection level, the refresh control signal level also changes to a non-refresh level. This state is maintained for a predetermined period. After the second chip enable signal changes from the selection level to the non-selection level, the refresh control signal returns from the non-refresh level to the refresh level. Thus, the PSRAM enters into the refresh state during the non-selection state, and is refreshed. This refresh operation is necessarily performed after an access to PSRAM.

A semiconductor memory having dynamic memory cells includes a determining circuit for determining whether or not it is necessary to refresh the dynamic memory cells, and only when it is necessary, outputting a refresh execution signal in response to a refresh request signal from an external circuit, and a circuit for executing a refresh operation in response to the refresh execution signal. Even if the refresh request signal is supplied, a refresh operation is not executed unless the determining circuit determines that the refresh operation is necessary, thus dispensing with unnecessary refresh operations. Preferably, the determining circuit includes a timer which outputs a signal at every predetermined period. Only when the signal is output from the timer, is the refresh request signal from an external circuit accepted and the refresh execution signal output.

Semiconductor memory

A virtual type static semiconductor memory device according to the present invention comprises a refresh detector circuit for detecting the enabling operation of a refresh control circuit and a terminal for outputting to an outside a detection signal which is generated from the refresh detector circuit. The virtual type static semiconductor memory device informs a present refresh operation to the outside when it is accessed from the outside during the time period in which a refresh operation is conducted in the semiconductor memory device. A system employing the semiconductor memory device allows a slow access at that time only and allows access to be gained to the semiconductor memory device at high speed at other times.

Growing community of inventors

Kawasaki, Japan

Hisashi Ueno