Kabushiki Kaisha Toshiba

Hitachi, Ltd.

Hisashi Sugiyama

Yasuhiro Sugimoto

Kazuo Nate

Akiko Mizushima

Takashi Inoue

Yoshihide Yamaguchi

Yukio Kamatani

Naoya Kitamura

Hideyasu Murooka

Makio Watanabe

Michinori Nakamura

Ryoji Iwamura

Takeshi Sugoh

Masayuki Kyoui

Keisuke Ebata

A semicustom integrated circuit comprises pads arranged on peripheral portions of a chip along the four sides thereof. Peripheral circuit cells are arranged on a part of the chip to the inside of the pads. An internal circuit is arranged on a part of the chip to the inside of the peripheral circuit cell. The peripheral circuit cells include an ECL level input circuit an ECL level output circuit, a TTL level input circuit and a TTL level output circuit. Main source lines are formed on the peripheral circuit cells so as to surround the internal circuit. The main source lines are connected to pads to which source potentials is applied. Branch source lines cross the main source lines and connected to a selected one of the peripheral circuit cells and said internal circuit. The main source lines are selectively connected to the branch source lines by an interlayer connecting source line.

Wiring structure of source line used in semicustom integrated circuit

A multilayer wiring board fabricating method and a multilayer wiring board fabricated with use of the method that a solvent-free fluid polymer precursor is put on a wiring layer of a base substrate, and space among the wirings is exhausted and is filled with the precursor, and the precursor is hardened under a hydrostatic pressure and then the next wiring layer is formed before the above process is repeated one or more times. The multilayer wiring board fabricating method is excellent in the mass productivity and low cost and in that the wiring can be made highly dense with the substrate having vertical via conductors for connection among the conductor layers.

Multilayer wiring board fabricating method

Disclosed herein is a photosensitive resin composition composed mainly of an alkali-soluble organometallic polymer and a photosensitive dissolution inhibitor. The composition is used as a positive type resist which can be developed with an alkali developing solution. The resist has high sensitivity, high resolution, and resistance to oxygen plasma.

Photosensitive resin composition having high resistance to oxygen

An .alpha.-diazoacetoacetic acid ester derived from cholic acid, deoxycholic acid, lithocholic acid or a derivative thereof is effective as a sensitizer in a photosensitive resin composition containing an alkali-soluble resin to form a resist for lithography using KrF excimer laser.

.alpha.-diazoacetoacetates and photosensitive resin compositions

A logic circuit outputs state signals of seven different kinds, on the basis of first, second and third digital signals. A first composite gate circuit outputs a logical OR among the first to third digital signals as a first state signal. A first gate circuit outputs a logical OR between the second and third digital signals as a second state signal. A second composite gate circuit is supplied with a logical AND between the first and second digital signals, and outputs a logical OR between the supplied logical AND and the third digital signal as third state signal. A third composite gate circuit is supplied with a logical OR between the first and second digital signals, and outputs a logical AND between the supplied logical OR and the third digital signal as a fifth state signal. A second gate circuit outputs a logical AND between the second and third digital signals as a sixth state signal. A fourth composite gate circuit is supplied with a logical AND between the first and second digital signals, and outputs a logical AND between the supplied logical AND and the third digital signal as a seventh state signal. The third digital signal is output as a fourth state signal without being processed. Each of the above circuits has an emitter coupled logic structure.

Logic circuit for use in D/A converter having ECL-type gate structure

An analog/digital converter circuit including a capacitor having a first end, to which an analog voltage is applied, and a second end, an input buffer circuit having an input terminal, connected to the second end of said capacitor, and an output terminal, a reference voltage generating circuit for generating a plurality of reference voltages having different voltage levels, a voltage comparator circuit having a plurality of voltage comparators for comparing the output voltage of the input buffer circuit with each of the reference voltages generated by the reference voltage generating circuit, and generating a digital signal corresponding to the comparison results, a decoder circuit for decoding the output of the voltage comparator circuit, and D.C. bias voltage selection/supply circuit for selecting one of the reference voltages of the reference voltage generating circuit and supplying the selected reference voltage as a D.C. bias voltage to the input terminal of the input buffer circuit.

Analog/digital converter circuit

A Booth's algorithm conversion circuit having first and second switches controlled by input signals QX and Q2X and receiving as input, signals X.sub.i of a logic level positioned in the i digit order of a multiplicand X and signal X.sub.i-1 of a logic level positioned in the i-1 digit order of multiplicand X. The outputs of the first and second switches are tied together and to ground via first and second transitors controlled by signals QX and Q2X, the first and second transistors conducting in an inverse relationship to the first and second switch circuits. The common output of the first and second switch circuits is input to an exclusive OR circuit which receives an additional logic 1 or logic 0 input signal to produce the Booth's converted output. The resulting number of circuit elements and gates provides a simplified, high speed and small circuit for producing the Booth's conversion.

Booth's conversion circuit

Level conversion circuit for converting ECL logic level signals to CMOS logic level signals. The level conversion circuit includes: a differential amplifier circuit, which has a bipolar transistor of which the base terminal is connected to an input terminal and a bipolar transistor of which the base terminal is connected to a bias source, and which selects a current path from a high voltage source to a low voltage source; an MOS type transistor whose conduction is controlled by current flowing through the collector terminal of one of said bipolar transistors; a P-channel MOS type transistor, connected between the high voltage source and an output terminal, whose conduction is controlled either by the collector terminal current flowing through the collector terminal of the other of said bipolar transistors or by the drain terminal current flowing between the source termial and the drain terminal of said MOS transistor; and an N-channel MOS type transitor, connected between the low voltage source and the output terminal, whose conduction is controlled either said collector terminal current or by said drain terminal current.

Level conversion circuit

There are provided an alkali-soluble siloxane polymer, an alkali-soluble silmethylene polymer, and an alkali-soluble polyorganosilsesquioxane polymer. They are useful as a photoresist for the fabrication of semiconductor devices. They are suitable for dry etching because of their superior resistance to oxygen plasmas.

Growing community of inventors

Yokohama, Japan

Hisashi Sugiyama