Pioneer Electronic Corporation

Pioneer Corporation

Hisashi Suganuma

Yoshiharu Ueki

Tadashi Kosuga

Reisuke Sato

Tomohisa Yokogawa

Tadashi Ogawa

Masanao Okatani

Haruo Kama

Yoshiaki Ishibashi

Hiroshi Onishi

It is an object of the present invention to provide an improved noise removal device having an improved noise removal precision. A second noise extracting unit extracts a noise of an IF signal, and outputs a second noise signal which is then smoothed by a second noise smoothing unit to produce a second noise-smoothed signal. A noise hold control signal generating unit compares the second noise-smoothed signal with the second noise signal to produce a noise hold control signal indicating an occurring position and an occurring period of the noise of the IF signal. A first noise extracting unit extracts a noise of an FM detection signal, and outputs a first noise signal. A noise hold unit holds the first noise signal in accordance with the noise hold control signal to produce a held noise signal which is then smoothed by a first noise smoothing unit to produce a first noise-smoothed signal. A hold control signal generating unit compares the first noise-smoothed signal with the first noise signal to produce a hold control signal indicating an occurring position and an occurring period of the noise of the FM detection signal. Subsequently, a hold unit operates to hold the FM detection signal in accordance with the hold control signal, thereby generating and thus outputting an FM detection signal not containing any noise.

Noise removal device

An adjacent interference removal device capable of providing an improved reception quality. An IF signal Sin having passed through an IF filter having a pass frequency band width of 200 kHz is supplied to a first narrow band filter having a pass frequency band width extending from a center frequency (carrier frequency) of the IF filter to +50 kHz, as well as to a second narrow band filter having a pass frequency band width extending from a center frequency (carrier frequency) of the IF filter to &#x2212;50 kHz. When an interference signal is contained in a first signal Soutputted from the first narrow band filter but not in a second signal Soutputted from the second narrow band filter, and when an interference signal is contained in a detection signal Sdgenerated by detecting the second signal Sin a detector and contained in the second signal Sitself but not contained in the first signal Sthe detection signal Sdgenerated by detecting the first signal Sin another detector is outputted by performing a switchover in a signal selecting unit.

Adjacent interference removal device

A noise canceller for removing noise components from an input signal includes a noise detector which detects a noise component of the input signal and outputs a hold signal which corresponds to duration of the noise component, a first hold circuit which outputs a sample value while holding the input signal during the duration of the noise component, an adder which adds a compensating signal to the sample value, a prediction filter which determines predicted values by performing filter operations on the outputs from the adder, a second hold circuit which outputs a predicted hold value while holding the predicted value during the duration of the noise component, a subtractor which subtracts the predicted hold value from the predicted value and outputs a result as the compensating signal, and a switch which supplies the compensating signal to the adder.

Noise canceller

A digital FM demodulation circuit which samples an input analog FM signal and digitally detects the sampled input signal has an arctangent circuit into which a second signal that is delayed from the sampled input signal by a constant time, and a third signal that is different in phase by 90 degrees from the second signal are input, and which outputs a corresponding arctangent value based on a result of a division of the two input signals. The arctangent circuit has: roundoff means for sequentially rounding the division result to one of plural typical values; and a ROM address unit for performing a control in which an arctangent value corresponding to the rounded typical value is selected from a ROM table containing arctangent values of the typical values, and the selected arctangent value is output.

Digital FM demodulation circuit

The present invention relates to a prediction filter that estimates the next sampled value from previously sampled values, and which provides an improved prediction filter that makes a prediction with little error, even for an input signal containing a frequency component close to one-half the sampling frequency. Concatenated delay circuits delay sampled values by a sampling time interval (T). Coefficient circuits multiply the outputs of the delay circuits by a certain value, and an adder sums the outputs of the coefficient circuits. Sampled values at time t=T, 0, -T, -2T, . . . are assumed to be y.sub.1, y.sub.0, y.sub.-1, y.sub.2, . . . and a predicted value at t=T to be&lt;y.sub.1 &gt;. These are used to generate new variables&lt;y1&gt;=y.sub.0, y.sub.0 =y.sub.-1, y.sub.-1 =y.sub.-2, . . . The new variables are then substituted into first- and second-degree prediction equations to produce a predicted value&lt;y.sub.1 &gt;, and the coefficient of each term of the equation for&lt;y.sub.1 &gt; is used as the multiplication factor of each coefficient circuit.

Prediction filter

A noise removing circuit for removing an impulse noise in a signal. An input selector switch receives a first signal and a second signal to selectively output the first and second signals. A polyphase sampling pulse generator outputs polyphase pulse trains. A plurality of sample-and-hold circuits are in cascaded connection to sample and hold the output of the input selector switch. Each of the sample-and-hold circuits is activated by pulses of a corresponding phase of the polyphase pulse trains to sample and hold a signal level being held on a preceding circuit. Each of a plurality of multipliers has a predetermined multiplication coefficient and outputs the signal level on each of sample-and-hold circuits multiplied with said predetermined coefficient. An adder adds up the outputs of the plurality of multipliers to produce the second signal.

Noise removing circuit

An automatic gain control circuit where the direct current potential levels of the gate and the source of a field effect transistor in a preamplifier stage are maintained substantially equal during automatic gain control. In the first embodiment, the gate of the field effect transistor is responsive to a high frequency input signal and the drain provides the amplified high frequency input signals as an output signal. The source is connected to electrical ground by an inductor and is connected to a voltage source having a voltage level controlled in accordance with the automatic gain control signal. The inductor acts to shunt to ground the direct current component of the supply voltage provided to the source. In the second embodiment, the gate of the field effect transistor is responsive to a high frequency input signal and the source is connected to electrical ground. The drain is connected to a voltage source having a voltage level controlled in accordance with the automatic gain control signal and provides the amplified high frequency input signal as an output signal. The d.c. levels of the gate and source are maintained substantially equal and the AGC signal maintains a substantially zero d.c. bias on the field effect transistor to thereby minimize distortion.

Automatic gain control circuit

A manual tuning pulse generator for use in an electronic tuning control device of a radio receiver having a tuning circuit, which control device utilizes an up/down counter, is disclosed which comprises a first manual means for selectively producing an up count signal and a down count signal to be supplied to the up/down counter, a second manual means ganged with said first manual means for producing a variable control signal and means responsive to the variable control signal to produce a clock pulse signal having a variable frequency, the pulses of the clock pulse signal being adapted to be counted up or down by the up/down counter the content of which is utilized to shift the tuning frequency.

Manual tuning pulse generator

The present invention is a magnetic tape running state and tape run amount display device which displays visually the running direction and speed or the run amount and direction of the magnetic tape. An up-down counter is provided with a clock input signal having a pulse generated in correspondence with the run of the tape and is also provided with a count control signal. The count control signal has an UP signal generated when the tape is being transported in a first or forward direction, and has a DOWN signal generated when the tape is being transported in a second or reverse direction. The up-down counter provides a binary output count signal to a display circuit in correspondence with the clock input signal and the count control signal. The up-down counter can also be provided with a reset input responsive to a reset signal which acts to reset the count back to logic 0. The display circuit provides a visual representation of the binary output signal, and may include a first binary-to-digital decoder and a second binary-to-digital decoder, each being responsive to a preselected portion of the binary bits provided by the up-down counter. A plurality of light emitting diodes are connected between decimal output lines of the first and second binary-to-digital decoders for providing a visual indication of the tape running state and run amount. In one arrangement, the diodes are arranged to define a line. The display circuit also can be responsive to the binary tuning signal provided by an electronic tuning type receiver.

Magnetic tape running state and tape run amount display device

An automatic gain control circuit where the direct current potential levels of the gate and the source of a field effect transistor in a preamplifier stage are maintained substantial equal during automatic gain control. In the first embodiment, the gate of the field effect transistor is responsive to a high frequency input signal and the drain provides the amplified high frequency input signals as an output signal. The source is connected to electrical ground by an inductor and is connected to a voltage source having a voltage level controlled in accordance with the automatic gain control signal. The inductor acts to shunt to ground the direct current component of the supply voltage provided to the source. In the second embodiment, the gate of the field effect transistor is responsive to a high frequency input signal and the drain is connected to electrical ground. The source provides the amplified high frequency input signal as an output signal, and also is connected to a voltage source having a voltage level controlled in accordance with the automatic gain control signal. The direct current levels of the gate and source are therefore maintained substantially equal.

The present invention is an electronic tuning type receiver having a band display unit and a numerical frequency display unit. The numerical frequency display unit provides a visual numerical display of the frequency selected by the receiver. The band display unit provides a visual indication of the relationship of the selected frequency with respect to the frequency band being tuned by the receiver.

Electronic tuning type receiver having a band display and numerical

A combination device having a magnetic recording and reproducing unit and an electronic tuning type receiver, where the channel presetting switches of the electronic tuning type receiver also can act as the operating switches of the magnetic recording and reproducing unit. The electronic tuning type receiver is of the type which is tuned by control signals provided to a tuning means by a plurality of channel selecting switches. A selection circuit is interposed between the tuning means and the plurality of channel selecting switches and provides the plurality of control signals to the tuning means when a selection switch is in a first binary state, and provides the plurality of control signals to a tape-control section when the selection switch is in a second binary state. The tape-control section, in response to the plurality of control signals, controls the mode of operation of the magnetic recording and reproducing unit, and also provides a signal indicating the mode of operation to a sensing circuit. The sensing circuit, in turn, provides mode signals to a digital display unit which can visually display the mode of operation when the magnetic recording and reproducing unit is being used, as well as can visually display the station frequency or the like of the selected station when the electronic tuning type receiver is being used.

Combination device having a magnetic recording and reproducing unit and

During preset station selection operation in a digital receiver the station selection switch most recently operated is indicated by a light so as to prevent erroneous operation at the same switch again.

Station selection indicating device

A preset state indicating unit for use in an electronic tuning type receiver generates a visual indication when both a presetting switch and one of a plurality of channel selecting switches have been properly selected. The preset state indicating unit thus insures that tuning information pertaining to a selected station is actually stored in memory during the presetting operation done by the user.

Preset state indicating unit in an electronic tuning type receiver

A temperature compensating circuit for a varactor diode having a voltage source applied to a temperature compensating diode which is provided separately from a control voltage for controlling the varactor diode and which is unaffected by a varactor diode controlling voltage source exhibiting a high impedance.

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Saitama, Japan

Hisashi Suganuma