Texas Instruments Corporation

Hisashi Shichijo

Chin-Yu Tsai

Zhiliang Julian Chen

Katsuo Komatsuzaki

Kuok Y Ling

Han-Tzong Yuan

Richard J Matyi

Baher S Haroun

Charvaka Duvvury

Krishnaswamy Nagaraj

Clarence W Teng

Keith Edmund Kunz

Venkatesh Srinivasan

Ih-Chin Chen

Hung-Dah Shih

Gaurav Chandra

Vijaya Bhaskar Rentala

Henry Litzmann Edwards

Amitava Chatterjee

Satwinder S Malhi

Seetharaman Sridhar

Byron Lovell Williams

Sanjay K Banerjee

Pallab K Chatterjee

Satyavolu Srinivas Papa Rao

Tathagata Chatterjee

Shyh-Horng Yang

Alwin J Tsao

Kenneth D Brennan

Kamel Benaissa

Darius Lammont Crenshaw

Alec James Morton

Lance Stanford Robertson

Albert H Taddiken

Steven Alan Lytle

Richard H Womack

John E Leiss

A drain extended MOS (DEMOS) transistor with an element of field oxide separating the drain contact from the gate, and a compensation region of opposite polarity in the drain under the gate, is disclosed. The inventive DEMOS may be fabricated in a CMOS IC without adding any process steps. Both n-channel and p-channel versions may be fabricated in CMOS ICs with an n-type buried layer. Furthermore, the inventive transistor may be fabricated in an IC built in an SOI wafer. The width of the compensation region may be varied across multiple instances of the inventive DEMOS transistor to provide a capability for handling multiple signals with different voltage levels in the same IC without adding fabrication steps. The compensation region may be biased by a control voltage to modulate the depletion of the drain extension and provide a capability for handling multiple signal voltage levels in a single transistor.

DEMOS transistors with STI and compensated well in drain

In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.

Process and temperature insensitive flicker noise monitor circuit

In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.

One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.

Matched analog CMOS transistors with extension wells

A method () of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer () is formed against an edge () of a layer of bottom electrode/copper diffusion barrier material (), an edge () of a layer of capacitor dielectric material () and at least some of an edge () of a layer of top electrode material. The sidewall spacer () is dielectric or non-conductive and mitigates 'shorting' currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material () mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.

Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode

A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

Device and method of low voltage SCR protection for high voltage failsafe ESD applications

A method for the fabrication of a light-sensing diode in a high-resistivity semiconductor substrate. A high-energy implant of ions into the substrate is patterned to form an annular well of the same conductivity type as the substrate; followed by a second high-energy implant of the opposite conductivity type, within the center of the annulus; followed by a third implant, of lower energy and high dosage, to form a region of the first conductivity type extending laterally near the substrate surface. The resulting diode junction is thereby patterned to include two planes near the substrate surface, allowing incident light to traverse the junction twice.

CMOS photodiode having reduced dark current and improved light sensitivity and responsivity

A light-sensing diode having improved efficiency due to an extended junction geometry that provides more than one level of interaction with the light input.

A light-sensing diode fabricated in a semiconductor substrate having a surface protected by an insulator, comprising a first region of one conductivity type in this substrate, a second region of the opposite conductivity type forming a junction with the first region in the substrate; this junction having a convoluted shape, providing two portions generally parallel to the surface, and a constricted intersection with the surface; and a gate for applying electrical bias across the junction, this gate positioned on the insulator such that it covers all portions of the junction intersection with the surface, thereby creating a gate-controlled photodiode.

Integrated CMOS structure for gate-controlled buried photodiode

Integrated structure for reduced leakage and improved fill-factor in CMOS pixel

A method for forming integrated circuit bipolar junction transistors for mixed signal circuits. The implants used to form the well regions of the CMOS circuits,form the collector regions of bipolar junction transistors. The CMOS transistor pocket implants form the base region of the bipolar junction transistor, and the CMOS drain extension implants form the emitter region of the bipolar junction transistor.

Integrated bipolar junction transistor for mixed signal circuits

Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs (110) on silicon (102) is accomplished by formation of a defect annihilating grid (104) on the silicon (102) prior to the epitaxy of the GaAs (110).

Epitaxial layer on a heterointerface

A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n- type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

Multiple substrate bias random access memory device

A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n-type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

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Plano, TX, United States of America

Hisashi Shichijo