Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Other

Hitachi Microcomputer Engineering, Ltd.

Hisashi Kaziwara

Shigeki Morinaga

Junichi Tatezaki

Takeshi Asai

Koyo Katsura

Shigeru Matsuo

Mitsuru Watabe

Hiroshi Takeda

Norio Nakagawa

Hiroyuki Kida

Shigeaki Yoshida

Yugo Kashiwagi

Tetsuaki Nakamikawa

Masahisa Narita

Shunpei Kawasaki

Atsushi Hasegawa

Ikuya Kawasaki

Makoto Hanawa

Kazuhiko Iwasaki

Takuichiro Nakazawa

Mamoru Ohba

A graphic processing system has a processor for managing a display area and a character font area both include within an are disposed in the address space. From coded information indicative of a character transferred through a data bus of the system, the processor generates an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area. The graphic processing system realizes high speed development of fonts.

Graphic processing system

A graphic processing system has a processor for managing a display area and a character font area both included within an address space. From coded information indicative of a character transferred through a data bus of the system, the processor generates an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area. The graphic processing system realizes high speed development of fonts.

Graphic processing system for displaying characters and pictures at high speed

A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.

Multiplication, division and square root extraction apparatus

A graphic processing system for text display which includes a data processing unit, composed of a memory and a processing unit, for creating character code information, and a graphic data processing unit, composed of a graphic data processor and a frame buffer, for creating pixel information. The text display is performed by creating character code information in the data processing unit, supplying the character code information from the data processing unit to the graphic data processor, creating addresses on the frame buffer corresponding to the character code information by the graphic data processor, reading out a character font from a second area of the frame buffer using the created addresses, writing the read-out character font in a predetermined position of a first area of the frame buffer, and outputting the display data at the first area of the frame buffer to a display unit.

System for obtaining strict solution in accordance with accuracy of

The interface portion of a coprocessor is provided with a FIFO (First-In First-Out) buffer and means for accepting instructions in succession. Pipeline control of the instructions becomes possible in this way, and protocol means associated with a microprocessor is also provided.

Coprocessor executing pipeline control for executing protocols and

A microcomputer system has a microprocessor and a number of independent coprocessors for executing individual instructions according to instruction data sent from the microprocessor. An address bus and a data bus interconnect the coprocessors with the microprocessor. The microprocessor sends instruction data to the coprocessors via the data bus and concurrently sends coprocessor designation data to the coprocessors via the address bus. The coprocessor designated by the designation data reads and reacts to the instruction data while the other coprocessors within the system disregard the instruction data.

System using microprocessor address lines for coprocessor selection

Graphic processing system for displaying characters and pictures at high

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Hitachi, Japan

Hisashi Kaziwara