Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Other

Hisashi Kajiwara

Koyo Katsura

Hideo Maejima

Naoki Mitsuishi

Hiroshi Saito

Koichi Hashimura

Hiromasa Yamagata

Kenji Takechi

A data processing apparatus which processes data held in memory. The data processing apparatus includes an address operation unit which obtains an address to read one-word data from the memory, wherein the one-word data is a unit of data access to the memory, and a logical operation unit which determines a content of an operation on a field basis based on information which designates the number of bits per field to construct one-word data with a plurality of fields having a same number of bits. The logical operation unit, based on the content thus determined, performs the operation in parallel on the fields of the one-word data read from the memory by the address thus obtained.

Graphic pattern processing apparatus

Two up-counters and two down-counters having a time difference corresponding to a dead time are provided to realize an up-down symmetric count, such that the up-counters and the down-counters are made to count the lower limit and the upper limit (a 1/2 period+the dead time), the up-counter for counting a relatively large value and the down-counter for counting a relatively large value are made to contact at the upper limit, the up-counter for counting a relatively small value and the down-counter for counting a relatively small value are made to intersect at a count value corresponding to the 1/2 period, the up-counter for counting the relatively large value and the down-counter for counting the relatively large value are made to intersect at the count value corresponding to the dead time, and the up-counter for counting the relatively small value and the down-counter for counting the relatively small value are made to contact at the lower limit.

Microprocessor having timer circuit generating complementary

A graphic data generating apparatus includes a data processor, a graphic memory, and a graphic processor. The data processor outputs instructions to the graphic processor for processing graphic data. The instructions include a drawing instruction for transferring graphic data stored in a predetermined location in the graphic memory to another predetermined location in the graphic memory. The graphic memory stores pixel data defining the graphic data and each of the pixel data having a plurality of bits. The graphic processor performing read out of word data having a plurality of pixel data at a word position of the graphic memory specified by a source memory address, selecting pixel data specified by a source pixel address in the readout word and writing the selected pixel data in the graphic memory at a pixel position specified by a destination pixel address of word data specified by the destination memory address.

A graphic pattern processing apparatus having a display memory, a data processor, a graphic processor, and a plurality of parallel to serial convertors. The display memory stores graphic data in words, each word has a plurality of pixel data and each pixel data has a plurality of bits. A graphic processor accesses the display memory and processes a plurality of the pixel data in response to instructions received from a data processor. The number of parallel to serial convertors corresponds to the number of bits per pixel and are configured to allow a word from the display memory to be converted into a serial stream of pixel data.

Graphic pattern processing apparatus having a parallel to serial

A graphic pattern processing apparatus having a graphic memory, a data processor, and a graphic processor. The graphic memory stores a pattern composed of pixel data. The graphics processor includes a plurality of color registers. The graphic processor reads the graphic memory in response to instructions received from the data processor. The graphics processor in response to the pixel data read from the graphic memory selects one of a plurality of color registers and outputs that value.

A graphic pattern processing apparatus for accessing a memory which stores words of graphic data. A plurality of pixels is stored in each word and each pixel has a plurality of bits. Each pixel of the word may be selected by a pixel address supplied by a graphic data processor. The graphic data processor performs processing on the selected pixel in accordance with instructions received from a data processor.

Graphic pattern processing apparatus for processing pixels havings a

A graphic data generating apparatus includes an output producing a graphic image having a plurality of bits; a display memory connected to the output for storing pixel data defining the graphic data for each of the pixel data having a plurality of bits; and a graphic data processing apparatus performing read out of word data having a plurality of pixel data at a word position of the display memory specified by a source memory address, selecting pixel data specified by a source pixel address in the readout word and writing the selected pixel data in the display memory at a pixel position specified by a destination pixel address of word data specified by the destination memory address.

A graphic data processing apparatus for accessing memory which stores pixels where each of the pixels is a picture element of a unique point in two-dimensional space and having a number of pixels which may be selected in the memory and for generating graphic data with two or more bits per pixel being used and a plurality of pixels of data being stored in one word of the memory is disclosed. A physical address operation unit stores information of a current drawing point including a memory address of a word in the memory and a pixel address defining a position of a pixel in one word specified by the memory address. A data operation unit modifies a particular pixel in the one word specified by the pixel address in accordance with a drawing instruction with a number of pixels within a word being selectable.

A graphic data processing apparatus is disclosed for accessing a memory which stores pixels having a number of bits which may be selected. Gaphic data is generated with one or more bits per pixel with a plurality of pixels of data being stored in one word of the memory. A physical address operation unit stores information of a current drawing point including a memory address of a word in the memory and a pixel address defining a position of a pixel in one word specified by the memory address. A data operation unit modifies a particular pixel having a number of bits which may be selected in the one word specified by the pixel address in accordance with a drawing instruction.

Graphic data processing apparatus for processing pixels having a number

A graphic pattern processing apparatus using a raster scan type CRT is disclosed. The graphic pattern processing apparatus can update one-pixel data, translate a logical address to a physical address and transfer data in a display memory, at a high speed. The graphic pattern processing apparatus comprises an operation unit including a logical address operation unit, a physical address operation unit, color data operation unit, and a control unit including a microprogram memory and a microprogram decoder.

Herein disclosed is a graphic processing apparatus which uses a CRT of raster scanning type. The graphic processing apparatus has functions to compare and judge whether or not within the range of a predetermined region thereby to effect the drawing operation, to compare drawing picture element data and other data in the drawing operation thereby to arithmetically control the drawing picture element data in accordance with the compared result, and to drawing a pattern of an arbitrary size on the basis of a fundamental unit of line and design patterns in the drawing operation.

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Hitachi, Japan

Hisashi Kajiwara