Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Engineering Company, Limited

Renesas Technology Corp.

Other

Hisashi Iwamoto

Yasuhiro Konishi

Katsumi Dosaka

Akira Yamazaki

Masaki Kumanoya

Kouji Hayano

Hideaki Abe

Yasuhiro Ishizuka

Katsumitsu Himukashi

Tsukasa Saiki

Yasumitsu Murai

Takashi Kubo

Takeshi Kajimoto

Wataru Sakamoto

Takashi Araki

Seiji Sawada

Naoya Watanabe

Takayuki Miyamoto

Aiko Nishino

Kenichi Yasuda

Junko Matsumoto

Nobuyuki Sato

Tsukasa Saika

A shift register which outputs a delay control signal for a delay line is made controllable at a test mode by a TEST MODE address buffer receiving an external address as a control signal and a phase comparator. Thus whether the delay of the delay line is correctly controlled or not can be confirmed through observation of an internal clock signal int. CLK output from an output buffer at the test and an external clock signal ext. CLK.

Semiconductor device allowing easy confirmation of operation of built in clock generation circuit

In a DLL circuit between a phase comparator and a digital filter there is provided a signal switching portion preventing control signals UP and DOWN from being transmitted after a clock enable signal extCKE is activated and before a predetermined period of time elapses. Thus after a semiconductor device returns from a power down mode and before a predetermined period of time elapses it continues to stop updating an amount of delay of a delay line. Thus before an internal power supply potential stabilizes the delay line does not have a varying amount of delay and as a result the semiconductor device can output data at a timing free of significant fluctuation.

Semiconductor device outputting data at a timing with reduced jitter

An impedance adjustment circuit generates an internal impedance adjustment signal and an impedance adjustment entry signal based on an externally applied impedance control signal. A data processing circuit decodes the internal impedance adjustment signal in synchronization with an internal clock signal to generate an output buffer drive signal of 5 bits. When the output buffer drive signal is applied to an output circuit of the succeeding stage as well as to an output replica circuit in a DLL circuit, the impedance of the output replica circuit is adjusted following adjustment of the output impedance.

Semiconductor device with clock generation circuit

A DLL circuit includes a delay line having a configuration with delay stages receiving alternate complementary clock signals ECK and /ECK having an adjusted phase difference therebetween. A capacitor can be used to adjust the phase difference between signals ECK and /ECK to allow the delay line to provide an amount of delay varying minutely. Preferably, for a fast clock, delay adjustment starts with a shift register having an initial value providing an intermediate amount of delay, and for a slow clock, delay adjustment starts with the shift register having an initial value providing a minimal amount of delay. There can be provided a semiconductor device provided with a DLL circuit accommodating a fast clock with reduced jitter.

Semiconductor device capable of generating highly precise internal clock

A clock buffer includes: a comparator circuit comparing complementary clock signals CLK and /CLK with each other to output an internal clock signal used in a normal operation; a comparator circuit comparing a reference potential Vref and clock signal CLK with each other; and a comparator circuit comparing reference potential Vref and clock signal /CLK with each other. A phase comparator circuit compares the complementary clock signals with each other in respect to phase. An input/output buffer outputs an output of the phase comparator circuit to a data output terminal in a test mode. Therefore, there can be realized a test mode for performing efficient calibration of a measuring apparatus.

Semiconductor device with test mode for performing efficient calibration of measuring apparatus

A semiconductor memory device is provided with a static random access memory (SRAM) serving as a cache memory and a dynamic random access memory (DRAM) serving as a main memory. A bi-directional data transfer circuit is arranged for transfer of data blocks between the SRAM and the DRAM. A command register is provided for holding command data to set operation modes such as a data output mode of the memory device. The data output mode may include a transparent mode, a latched mode and a registered mode selected depending on a data combination at data input terminals of the memory device. An output circuit for providing a selected data output mode includes an output latch circuit for latching data on read data buses in response to clock signals, and an output buffer for outputting data from the output latches to a data output terminal. The latch circuit provides data at a first clock cycle of a clock signal when the command data has a first value and provides data at a second clock cycle of the clock signal, which is later than the first clock cycle, when the command data has a second value.

Synchronous semiconductor memory including register for storing data input and output mode information

Serial write data of the burst length transmitted to a data bus are stored in parallel in latch circuits by a S/P data conversion circuit. In a memory cell array, one row of memory cells and four columns of memory cells are rendered active at the same time. Respective bit lines and latch circuits are connected by a sense amplifier I/O circuit. The write data of the burst length are written into the memory cell array at one time. The data of the bit length read out at one time from the memory cell array are converted into serial data by a P/S data conversion circuit to be transmitted to the data bus.

Semiconductor memory device capable of high speed input/output of wide bandwidth data by improving usage efficiency of external data bus

A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

Semiconductor memory device

There are provided a memory controller, a plurality of memory modules, and an external data bus common to the plurality of memory modules. The plurality of memory modules each include a plurality of memory chips, a plurality of internal data buses connected between a corresponding memory chip and an input/output terminal, a logic chip, and a plurality of switch transistors each connected between a corresponding internal data bus and a corresponding input/output terminal to turn on/off in response to a control signal from the logic chip. The plurality of switch transistors in a memory module selected by the memory controller are turned on, and the plurality of switch transistors in the memory modules other than the selected memory module are turned off. Thus, the capacity of the memory modules may be increased while maintaining high-speed data transfer.

Memory module system having multiple memory modules

A semiconductor memory device receives an external control signal repeatedly generated independently of an access to the memory device. The memory device includes an internal voltage generator for generating a desired internal voltage in response to the control signal. The internal voltage generator includes a charge pump circuit responsive to the control signal. The internal voltage may provide a negative voltage such as a substrate bias voltage, or may be a positive voltage boosted over an operating power supply voltage and used as a boosted word line drive signal. This scheme eliminates an oscillator for generating a repeated clock signal to the charge pump circuit, leading to reduced current consumption and reduced chip area for the semiconductor memory device.

Semiconductor memory device with an internal voltage generating circuit

An internal clock signal generating circuit includes a selector, a delay line, a 2-frequency divider, a phase comparator and a shift register. The selector alternately selects an external clock signal and an internal clock signal output from the delay line and outputs the selected signal to the delay line. The delay line receiving the signal delays the external clock signal, and delays the internal clock signal output from itself. The 2-frequency divider divides frequency of the internal clock signal by 2. Phase comparator compares phases of the external clock signal and the output signal from the 2-frequency divider. Delay time of the delay line is adjusted by the phase comparator and the shift register so that the phase difference is made 0.

Internal clock signal generating circuit having function of generating internal clock signals which are multiplication of an external clock signal

Input buffer for supplying semiconductor device with internal signal based on comparison of external signal with reference potential

A semiconductor memory device is configured to include a static random access memory (SRAM) array and a dynamic random access memory (DRAM) array. The memory device includes an internal data line which enables the transfer of data blocks between the SRAM and DRAM arrays. Data transfer circuitry is provided separately from the internal data line and includes a latch circuit for latching the data to be transferred. The data transfer circuitry is responsive to a transfer designating signal.

Semiconductor memory device and data transfer circuit for transferring data between a DRAM and a SRAM

A synchronous semiconductor memory device includes a prefetch selector receiving first and second data respectively read from first and second memory cells corresponding to even and odd addresses for outputting them to a data input/output terminal. The prefetch selector sequentially outputs first and second data to the data input/output terminal in one period of a clock period in the normal operation, determines if the first and second data match in a test mode, and outputs the determination result to the data input/output terminal in one period of the clock period.

Synchronous semiconductor memory device which can be inspected even with

A synchronous semiconductor memory device capable of improving substantial transfer rate is provided. In response to a write command immediately following an act command, a control signal generating circuit applies an inactive enable signal to a read preamplifier & write buffer. In response to a write command and a precharge command, the control signal generating circuit generates an active enable signal, and the read preamplifier & write buffer writes the data stored in an FIFO to a memory cell. As late write is not performed upon reception of a write command immediately following an act command, erroneous writing of data to a not intended address can be prevented.

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Hyogo, Japan

Hisashi Iwamoto