Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Fujitus Limited

Hisao Suzuki

Yoshiaki Shimizu

Shogo Itoh

Masashi Kijima

Kenji Ito

Katuyuki Yasukouchi

Osamu Kobayashi

Tomoya Kakamu

Yuji Sekido

Norikazu Fushimi

A digital-to-analog (D/A) converter includes first resistors coupled in series, second resistors respectively coupled to the first resistors and each having a resistance twice as large as the resistance of the first resistor, and first switch circuits respectively coupled to the second resistors. Third resistors each have a resistance twice as large as the resistance of the first resistor. Second switch circuits each are coupled to the third resistors and a GND wire. A control circuit controls the first and second switch circuit in accordance with the digital input signals to set a state of a connection node to either one of a first voltage, a second voltage, and a high impedance.

D/A converter

A digital-to-analog (D/A) converter includes D/A conversion circuits and an amplifier circuit coupled between the D/A conversion circuits. Each D/A conversion circuit includes an R-2R ladder type resistor network, first transistors coupled between the resistor network and a first wiring at a first voltage level, and second transistors coupled between the resistor network and a second wiring at a second voltage level. The sizes of the first transistors are set at a ratio of powers of 2. The sizes of second transistors are set at a ratio of powers of 2. The second transistors are respectively turned on and off complementarily to the first transistors according to the digital input signal.

A first conversion circuit converts a first clock signal based on a signal level of a first voltage into a second clock signal based on a signal level of a second voltage. A flip-flop circuit supplied with the first voltage as an operation voltage latches and outputs a signal, which is based on the signal level of the first voltage, in accordance with the first clock signal. A second conversion circuit supplied with the second voltage as an operation voltage converts a signal level of an input signal, which is based on an output signal of the flip-flop circuit, into the signal level of the second voltage in synchronization with the second clock signal.

Level conversion circuit and semiconductor device

An operational amplifier includes a first amplifier to which an input signal is applied, and a second amplifier to which an output of the first amplifier is applied, wherein the second amplifier includes a first transistor including a gate to which the output of the first amplifier is applied, and a second transistor including a gate to which the output of the first amplifier is applied, and a drain coupled to a source of the first transistor.

Operational amplifier

A D/A conversion circuit for performing D/A conversion at high speeds. The D/A conversion circuit includes a resistor string including a plurality of resistor elements connected between a low-potential power supply and a high-potential power supply. A plurality of first switch groups are connected to the connection nodes between the resistor elements for selectively outputting voltages at the connection nodes. The outputs of the switches of the first switch groups are connected in common to a corresponding one of the nodes. The plurality of nodes are connected to an output terminal of the D/A conversion circuit via a second switch group. Predetermined switches of the first switch groups are connected in parallel to third switches to apply voltages to the nodes.

A/D conversion circuit for use with low-potential and high-potential power supplies

An A/D conversion circuit including a plurality of resistor elements connected in series between a low-potential power supply and a high-potential power supply. The A/D conversion circuit includes a plurality of comparators that compare a reference voltage divided by each of the resistor elements with an analog input voltage, the comparators having a sample-and-hold function for holding a sampled analog input voltage. The plurality of comparators also include a high-order bit comparator and a low-order bit comparator having different sampling sources. The high-order bit comparator may be configured to compare the analog input voltage and one of the reference voltages to obtain a determination result. The low-order bit comparator may old the analog voltage from the time that the low-order bit comparator retrieves the analog input voltage until the low-order bit comparator performs comparison.

A differential amplifier circuit of simple circuit configuration is disclosed, which is capable of releasing an output signal within a voltage range independent of the voltage range of a differential input signal. The differential amplifier circuitincludes: NMOS transistors N, Nthat constitute a first differential pair configured to input a differential input voltage; a resistor element Ra connected to drain terminals X, Xof the NMOS transistors N, N; an op-amp OP having input terminals connected to the drain terminals X, X; and NMOS transistors N, Nthat constitute a second differential pair configured to input an output voltage of the op-amp OP and a reference voltage. The drain terminals of the first differential pair are connected to drain terminals, respectively, of the second differential pair.

Differential amplifier circuit

A digital-analog converter including a first selection circuit of switch elements, which are coupled to each other and to a high potential power supply, and a second selection circuit of switch elements, which are coupled to each other and to a low potential power supply. First and second voltage dividing circuit each include series-connected resistor elements, each coupled between adjacent switch elements of the corresponding selection circuit. A control circuit provides a control signal to the selection circuits to activate one of the switch elements in each selection circuit and couple the activated switch element to the corresponding potential power supply. The first and second voltage dividing circuits divide voltages of the high and low potential power supplies with the resistor elements between the activated switch elements.

A level shift circuit for sustaining the activation and inactivation response of a transistor with respect to an input signal in a preferable manner. The level shift circuit includes a shift circuit for converting an input signal having a first voltage to an output signal having a second voltage that is higher than the first voltage. The voltage generation circuit includes a control voltage generation circuit, for generating control voltage having a generally constant voltage level irrespective of the level of a power supply voltage, and a bias generation circuit. The bias generation circuit generates bias voltage so that the node voltage of the shift circuit is substantially equalized with the control voltage.

Level shift circuit and semiconductor device

D/A conversion circuit and A/D conversion circuit

A level shift circuit including a capacitor, a charge control circuit, and a limiting circuit. The charge control circuit is connected to the capacitor to provide the voltage of a high potential power supply to the capacitor and to control the charging of the capacitor. The limiting circuit is connected to the high potential power supply and the charge control circuit to limit the voltage provided to the capacitor from the high potential power supply before the charge control circuit stops providing the voltage of the high potential power supply to the capacitor.

A compact and highly accurate A/D converter includes series-connected computation cells, the number of which is equal to the number for bits in an output signal. The first computation cell includes a first comparison unit for subtracting a reference current from a first input current to generate a first current, and a second comparison unit for subtracting a second input current from the reference current to generate a second current. The second computation cell includes first and second comparison units having the same configurations as those in the first computation cell. The computation cells of latter stages have the same configurations as the second computation cell. Current mirror circuits included in the first and second comparison units of each computation cell generate the first and second currents. Each computation cell outputs a current having an absolute value in accordance with one of the first and second currents.

A/D converter

Provided is a digital-analog converter circuit that enables, for example, securing an improved accurate analog signal voltage and preventing increase in the circuit size. A first node of each individual unit is connected to a middle node of a one-order higher unit than a unit having that first node. A second node of the each individual unit is connected to one of the first and second nodes provided in the one-order higher unit than the unit having that second node, the one being on the side connected to a resister section set to an impedance valueZ. A hierarchical structure can be formed in which an opponent connection point of the second node is selected by a hierarchy switch section, whereby the each individual unit is parallel connected to the resister section provided in the one-order higher unit and set to the impedance valueZ. In correspondence to an input first-order bit signal (D), an analog signal voltage (AV) corresponding to an output code () of digital data is output from a lowest-order bit unit (LU). In this manner, the D-A conversion operation is performed.

Digital-analog converter circuit

A current mode A/D converter for reducing current consumption while enhancing resolution. The A/D converter includes a V/I conversion circuit for sampling and converting an input voltage to a current, an I/V conversion circuit for converting the current supplied from the V/I conversion circuit to a comparison voltage, a comparator for comparing the current based on the comparison voltage and a reference current, and an encoder for generating a digital output signal based on the output signal of the comparator.

It is intended to provide an A/D converter circuit with which, by using a clock signal, on the basis of an analog voltage inputted a predetermined time past, it is possible to select suitably comparators to be operated and comparators to be rested, and which has small consumed power. A parallel-type A/D-converter circuitconverts an analog voltage VIN to a digital value DOUT at intervals of a predetermined period by means of a clock signal CLK using chopper-type comparators. The comparatorscan each be set by first and second setting signals CONTA etc. to either of an operating state and a resting state. A comparator control circuit sectionperforms logical processing on the comparator outputs OUT&#x2013;OUTin the preceding conversion to generate the first and second setting signals CONTA etc., and brings some of the comparators to the operating state and holds the remaining comparators in the resting state.

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Kasugai, Japan

Hisao Suzuki