Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Device Eng. Co., Ltd.

Hisao Katto

Kousuke Okuyama

Kazuyuki Miyazawa

Masamichi Ishihara

Hidetoshi Iwai

Tetsuro Matsumoto

Kazumichi Mitsusada

Akira Endo

June Sugiura

Nozomi Horino

Yuji Arakawa

Yoshiharu Takeuchi

Kazuhiro Komori

Satoshi Meguro

Jun Sugiura

Ken Uchida

Kouichi Kusuyama

Toshio Sasaki

Yoshio Sakai

Isao Yoshida

Toshiaki Masuhara

Osamu Minato

Masatada Horiuchi

Minoru Nagata

Norikazu Hashimoto

Shin-ichi Muramatsu

Shikayuki Ochi

Akihiro Tomozawa

Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

Method of fabrication of semiconductor integrated circuit device

A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.

Method of making a semiconductor memory device

Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implantation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

Semiconductor integrated circuit device having output and internal

Semiconductor integrated circuit device having a first MISFET of an

Semiconductor integrated circuit device having input protective elements

Semiconductor memory device with additional conductive line to prevent

A heavily-doped semiconductor region and a channel stopper region, which are disposed under a memory cell in a memory cell region, are simultaneously formed after formation of a field insulator film, thereby preventing the channel stopper region from oozing out into the channel region, and thus obtaining a semiconductor memory device which is resistant to .alpha.-rays and therefore free from soft errors caused by .alpha.-rays. Also disclosed is a method of producing said semiconductor memory device.

Method of producing semiconductor memory device

Disclosed is a semiconductor device having an internal circuit protected by an electrostatoc protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

Semiconductor integrated circuit device having protective/output

Method of producing semiconductor memory device with buried barrier layer

Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced. Furthermore, there is disclosed a memory structure of a semiconductor memory device suitable for a higher degree of integration through an arrangement of gate electrodes of multiple layers.

Method of making a read only memory device

Semiconductor device and manufacturing method thereof

Semiconductor memory device with means to prevent word line breakage

A semiconductor integrated circuit device wherein the source and drain regions of a MOSFET in an internal circuit have lightly doped drain (LDD) structures in order to suppress the appearance of hot carriers, and the source and drain regions of a MOSFET in an input/output circuit have structures doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

Semiconductor integrated circuit device

A semiconductor memory device wherein a portion of source region of a field-effect transistor that serves as a memory cell has a low impurity concentration, so that hot carriers generated on the source side are injected into the floating gate. Hot carriers are generated by utilizing a large electric field intensity established by the drop of voltage in the region of low impurity concentration. The voltage difference is so great between the source region and the control gate that hot carriers generated on the source side are efficiently injected into the floating gate.

Semiconductor memory device

Growing community of inventors

Hinode, Japan

Hisao Katto