Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Engineering Company, Limited

Hisao Katoh

Yoshifumi Imanaka

Takeyasu Nakai

Input data is converted into digital data in a A/D converter in synchronization with a regenerated clock, a zero-cross detecting signal of the digital data is detected in a zero-cross detector, a phase shift quantity is detected in a phase detector according to two pieces of digital data obtained before and after the detection of the zero-cross detecting signal, an average of phase shift quantities is calculated as target oscillation frequency data in a frequency calculating unit, the target oscillation frequency data is converted into analog data in a D/A converting unit, and the regenerated clock is generated in a voltage control oscillator according to the analog data and is provided for the A/D converter. Thereafter, the digital data is decoded to regenerated data in a Viterbi decoder in synchronization with the regenerated clock. Accordingly, because the constituent elements between the A/D converter and the D/A converter can be made of digital circuits, the information regenerating apparatus does not receive an adverse influence in which characteristics of analog circuits lack uniformity, and the information regenerating apparatus, which is operated at a uniform characteristic and has a high performance, can be obtained.

Information regenerating apparatus and information regenerating method

A phase comparator circuit reducing the effects of offset and jitter, and a data Phase Locked Loop circuit incorporating the phase comparator circuit. The phase comparator circuit includes a Delay Locked Loop circuit for outputting a delay, signal PLDTD with a delay according to an oscillation frequency of a voltage controlled oscillator, with respect to an input data PLDT, a D-type flip-flop for outputting a delay signal PLDTL by latching an input data PLCK according to an oscillation clock PLCK output from a voltage controlled oscillator, and a phase comparator for comparing phases of delay signals PLDTD and PLDTL.

Data phase locked loop circuit

An optical disc device is provided with a channel phase-locked loop (channel PLL) for generating a read clock signal and a wobble phase-locked loop (wobble PLL) for generating a write clock signal. A frequency divider divides the frequency of the write clock signal from the wobble PLL by a predetermined number n so as to generate a pseudo channel data. A selector selects the pseudo channel data and then furnishes the selected pseudo channel data to the channel PLL when the optical disc device handles a not-yet-recorded area between two adjacent header areas on an optical disc where no data is recorded. The channel PLL locks itself with the pseudo channel data from the selector.

Optical disc device

A voltage controlled ring oscillator has a current control circuit and an odd number of inverter circuits. Each inverter circuit has a current charge preventing circuit connected between a ground voltage and a connection node located between a current source transistor and a complementary transistor circuit and a current discharge preventing circuit connected between a high voltage power source and a connection node located between a current source transistor and a complementary transistor circuit.

Growing community of inventors

Tokyo, Japan

Hisao Katoh