Fujitsu Corporation

Imec

Hisanori Fujisawa

Miyoshi Saito

Hiroshi Furukawa

Shiro Uriu

Tetsuo Kawano

Ichiro Kasama

Mitsuharu Wakayoshi

Kazuaki Imafuku

Hirotaka Tamura

Tetsu Tanizawa

Toshihiro Ozawa

Jason Helge Anderson

Hideki Yoshizawa

Teruo Ishihara

David Thach

Hiroaki Fujimoto

Paul Coene

Safeen Huda

Hideki Yosizawa

An information processing apparatus has a processor and a programmable logic circuit device (PLD) that includes a reconfiguration region to configure a logic circuit requested by a configuration request from the processor. The processor compares a first execution time of a plurality of the logic circuits for a case when a degree of parallelism adjustment is performed by decreasing a degree of parallelism of a first logic circuit and increasing a degree of parallelism of a second logic circuit and a second execution time of the plurality of logic circuits for a case when the degree of parallelism adjustment is not performed, and requests the degree of parallelism adjustment to the PLD when the first execution time is shorter than the second execution time, and does not request the degree of parallelism adjustment to the PLD when the first execution time is not shorter than the second execution time.

Information processing apparatus, PLD management program and PLD management method

A semiconductor integrated circuit includes: a first wire through which a signal is transmitted; a second wire that is not used for signal transmission; a switch that creates or breaks an electric connection between the first wire and the second wire; and a control circuit that controls the switch according to an potential of the signal, which is transmitted through the first wire, so that part of charge stored in a first wire capacitor of the first wire moves to a second wire capacitor of the second wire and is stored in the second wire capacitor and the charge stored in the second wire capacitor are drawn to the first wire capacitor to charge the first wire capacitor.

Semiconductor integrated circuit

The reconfigurable circuit of the present invention in which time division multiple processing is possible has a pipeline structure with the number of stages of an integral multiple of a given number, and comprises a plurality of processor elements having a processing unit whose configuration is variable according to first configuration data to be supplied, a network in which all inputs and outputs of a plurality of said processor elements are connected and which transfers data by one clock between the input and output according to second configuration data to be supplied, and a switching unit which cyclically switches by one clock and supplies the first and second configuration data prepared for the given number of tasks to each of the processing units.

Reconfigurable circuit having a pipeline structure for carrying out time division multiple processing

A serial data processing circuit that realizes the same performance as that of the pipeline processing with low power consumption. First to fourth latch units receive, in parallel, data sets supplied to a logic circuit. These latch units sequentially latch the data sets sequentially supplied to the logic circuit and output N data sets in parallel. A Selector sequentially selects the data sets supplied from these latch units and supplies the selected data sets to the logical circuit. For example, when the first latch unit latches data (a), the selector selects the data (a) and supplies it to the logic circuit. When the second latch unit latches data (b), the selector selects the data (b) and supplies it to the logic circuit. The logic circuit processes N serial data sets during each cycle.

Serial data processing circuit

A system for mapping tasks of at least one application on processing units of a reconfigurable array, the system comprising a plurality of programmable processing units, each programmable processing unit having at least one connection node, the programmable processing units disposed on a layer permitting interconnection between connection nodes; and a mapping unit adapted to substantially simultaneously optimize placement of the tasks on the plurality of programmable processing units and routing of interconnections between the plurality of processing units, the mapping unit adapted to select one placement algorithm among a plurality of predetermined placement algorithms and to select one routing algorithm from a plurality of predetermined placement algorithms, the selection configured to prefer use of non-random algorithms.

System and method for runtime placement and routing of a processing array

A reconfigurable circuit and control method therefor, capable of enhancing efficiency of implementation of a pipeline process in processing elements and improve processing performance. Processing elements are reconfigured to form a circuit based on configuration information and execute a prescribed process. Memory units store configuration information for the processing elements. A memory switching unit switches the plurality of memory units to store therein the configuration information on the stages of a pipeline process to be performed by the processing elements. A configuration information output unit switches the memory units to output therefrom the configuration information to the plurality of processing elements.

Alternately selecting memory units to store and retrieve configuration information in respective areas for a plurality of processing elements to perform pipelined processes

An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.

Data buffer control which controls selection of path and operation of data buffer, based on stored configuration information

A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Array processor having reconfigurable data transfer capabilities

The present invention provides a reconfigurable processing apparatus enabling clusters to utilize a shared functional unit by using data and a validity signal received from the clusters by way of a network therebetween. In the reconfigurable processing apparatus comprising one or more clusters which are reconfigured based on configuration information, the shared functional unit accepts an input data and an input valid signal from the clusters, the input valid signal starts up the shared functional unit so as to operate the input data received with the input valid signal and output, to the cluster, an output data as the operation result and an output valid signal for notifying of the cluster as an output destination of the aforementioned output data.

Reconfigurable processor

An operation apparatus includes a plurality of operation device units; a configuration memory storing setting information provided for each predetermined state of the plurality of operation device units; and a sequencer controlling the plurality of operation device units by outputting transition destination addresses designating relevant information from configuration information comprising the setting information provided for each state of the operation device units stored in the configuration memory, wherein the sequencer carries out operation based on task information previously loaded and a change-over condition signal output from the plurality of operation device units, and generates the transition destination address to output to the configuration memory.

Operation apparatus having sequencer controlling states of plurality of operation units and operation apparatus control method therefor

An arithmetic unit capable of reconfiguring circuitry in accordance with configuration data supplied includes a data processing unit performing a processing using input data; an output data maintenance unit maintaining the result of the processing to output it as an output data; and an output valid signal control unit outputting an output valid signal indicating whether or not the output data is valid, in which an output timing of a valid data to outside the arithmetic unit can be controlled optionally by controlling the output timing of the output valid signal.

Reconfigurable semiconductor device capable of controlling output timing of data

An integrated circuit apparatus includes a reconfigurable arithmetic operation device and a control device that generates mapping data defining a circuit configuration of the reconfigurable arithmetic operation device whose circuit configuration is changed while a given application is running and another application is newly implemented and run. The control device generates mapping data defining an intermediate configuration to shift from a circuit configuration defined by first mapping data to a configuration defined by final mapping data through the intermediate configuration.

Integrated circuit apparatus

A network structure configures a blocking network having constraint against such a combination of said network input terminal and network output terminal as to make it unfeasible to further connect, when connecting first network input terminals to first network output terminals, second network input terminals to any one of the second network output terminals, and operation elements and the network output terminals are connected so as to minimize a constraint strength between the plurality of network output terminals inputting to the same operation element with respect to the constraint strength defined as the number of network input terminals contained in tuples of network input terminals to which the two network output terminals in the network output terminals can not be simultaneously connected.

Circuit and circuit connecting method

In a method and apparatus for carrying out circuit simulation which performs circuit simulation on a circuit to be simulated, a plurality of partial circuits to be inspected for equivalence in order to check if they exhibit equivalent operational characteristics are extracted from the circuit to be simulated, and the intensity of the influence of an external terminal of the circuit to be simulated is assessed by tracing paths linking the external terminal and given terminals of the partial circuits. Moreover, based on the configurations of the partial circuits, the connectional relationships of corresponding input terminals of the partial circuits, the operational characteristics of corresponding component elements of the partial circuits, and the intensity of the influence of the external terminal, the plurality of partial circuits are inspected for equivalence in order to detect partial circuits exhibiting equivalence. After the circuit to be simulated is compressed by integrating the partial circuits into one circuit, circuit simulation is carried out.

Method and apparatus for carrying out circuit simulation

Paths from a block that includes the node that is the object of analysis to another block are searched for by a path search section for all blocks in a circuit; and a depth judgment section finds the depth of each block from that path search information. An effective block judgment section compares the depth of each block to a specified depth that is stored in a specified depth storage section, and judges which blocks are effective blocks. Thus, blocks that include nodes that exert influence on the simulation accuracy at the node that is the object of analysis are extracted from the circuit that is the object of simulation as effective blocks. Then, in the circuit simulation, events are generated only for the effective blocks, and a transient analysis simulation is executed by the event-driven method. This permits the processing speed of the simulation to be increased while maintaining accuracy.

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Kawasaki, Japan

Hisanori Fujisawa