Sony Corporation

Hisanobu Tsukazaki

Hironobu Mori

Katsutoshi Moriyama

Patrick Chuang

Katsuya Nakashima

Yoshifumi Miyazima

The object of the present invention is to provide a composite storage circuit capable of executing a writing operation and reading operation at high speed, and as the result of that, a semiconductor apparatus capable of realizing an instant-on function and an instant-off function is provided. The composite storage circuit is constituted of a volatile storage circuit and a non-volatile storage circuit connected in parallel, and the same information as storage information in the volatile storage circuit is stored in the non-volatile storage circuit. Moreover, as a power supply to the volatile storage circuit decreases, storage information in the volatile storage circuit is written in the non-volatile storage circuit. Further, after a power failure or a decreased power supply, storage information from the non-volatile storage circuit is returned to the volatile storage circuit upon restarting power feeding. Further, a semiconductor apparatus is constituted by having the composite storage circuit described above.

Composite storage circuit and semiconductor device having the same

It is an object to provide, in a data storage circuit for storing data, a power saving data storage circuit and a data writing method in the data storage circuit, and, further, to provide a data storage device. Thus, in the present invention, reading out existing data stored in a storage element M is performed prior to performing writing of new data to the storage element M to compare the existing data and the new data. The data storage circuit is configured so that in a case where the existing data and the new data are identical with each other, writing to the storage element M is not performed, and, in a case where the existing data and the new data are not identical with each other, writing of the new data to the storage element M is performed. The data storage circuit is formed on a semiconductor substrate to have a data storage device.

Power saving data storage circuit, data writing method in the same, and data storage device

An address transition detector (ATD) detects a change of address and generates a pulse signal Sc. A control circuit generates a pulse signal Sd and outputs it to a booster circuit in response to a timing of completion of the signal Sc. The booster circuit generates a boosted voltage higher in level than a power supply voltage during an active period of the signal Sd and outputs it to a decoder. The decoder holds the control gate of the output transistor connected to the word line selected in response to the address at a first voltage level, then inputs the boosted voltage to one of the source and drain electrodes so as to hold the gate at a second voltage level higher than the first voltage level by exactly the boosted voltage using capacitive coupling between the control gate and the one of the source and drain electrodes, whereby it outputs a boosted voltage to the other of the drain and source electrodes and drives the word line connected to the other of the drain and source electrodes. Since a boosted voltage higher than the power supply voltage is supplied to the selected word line, the write operation can be carried out reliably and deterioration of the data holding characteristic of the memory cell due to the reduction of the power supply voltage can be prevented.

Word line voltage supply circuit

A memory device comprising a memory cell for storing data, at least one bit line connected to the memory cell, and a switch normally held in a first condition connecting the bit line to a voltage source. The switch is in a second condition disconnecting the bit line from the voltage source in the presence of a control signal. The memory device also includes a program device for producing the control signal to change the switch from the first condition to the second condition when the bit line has a leakage trouble.

Growing community of inventors

Nagasaki, Japan

Hisanobu Tsukazaki