Fujitsu Corporation

Nippon Telegraph and Telephone Corporation

Hisamitsu Tanihira

Yuji Shibata

Makoto Okazaki

Kazuo Nagahori

Renri Nakano

Yoshiaki Wakimura

Katsuyuki Okada

Data for designating a status mode is written beforehand in a data portion of a data-type microinstruction. When power is introduced, first, the data type microinstruction is read. Next, a status-mode setting circuit generates an enable signal. The enable signal is only generated at the initial reading of the data-type microinstruction. The status-mode designating data written in the data portion of the microinstruction is stored in a status-mode memory in response to the enable signal. A central processing unit reads the status-mode designating data that has been stored in the status-mode memory and executes processing conforming to the status mode read.

Method and apparatus for setting the status mode of a central processing

A bus interface system has a bus interface, a common memory, a local bus, and a memory controller for use in a memory control. The memory controller has a buffer and is connected to the local bus. The bus interface has a burst disassembling control circuit which disassembles burst transfer data into one or a plurality of block transfers and one or a plurality of one-word transfers, which are supplied to the memory controller so that when the bus interface receives all requested data received from the common memory during a read access, the bus interface adds information on a destination device, connected to a system bus, to all the requested data and sends all the requested data with that information to the destination device via the system bus.

Bus interface structure and system for controlling the bus interface

A data shifting circuit comprises a barrel shifter for shifting by a plurality of bits data having a width twice that of a certain data width, and a data controller for supplying the same data having the certain data width commonly to the most significant bits and the least significant bits of the barrel shifter means.

Data shifting circuit capable of an original data width rotation and a

A bus arbiter permits an answer transfer request to utilize a system bus with higher priority than a command transfer request, thereby increasing the processing efficiency of CPU boards. A multi-processor system utilize the system bus with a time split transfer system in which the data width of a unit is inserted into a command and an answer transmitted and received between processors and transmitted as bus width information, thus making it possible to interconnect a unit, which processes data of an arbitrary data width, to the system bus. Local memories of a plurality of units connected to the system bus can be accessed via a bus interface of an input and output unit.

Bus control system in a multi-processor system

In a system for testing an instruction queue circuit connected to an external memory via a bus controller provided in a processor having a microprogram control unit, an operation unit connected to the microprogram control unit and connected, via an internal bus, to the instruction queue circuit, the instruction queue circuit-including a plurality of queue buffers, a writing unit writes internal bus information transferred via the internal bus into the instruction queue circuit in response to a first instruction generated by the microprogram control unit. The internal bus information is contained in the first instruction. A reading unit reads the internal bus information from the instruction queue circuit in response to a second instruction generated by the microprogram control unit. A gate circuit outputs the internal bus information to the internal bus in response to a third instruction generated by the microprogram control circuit. The internal bus information is used to test the instruction queue circuit.

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Kawasaki, Japan

Hisamitsu Tanihira